Parity Checker

A parity checker sits at the receiver end of every UART and SPI link to catch corrupted bytes before they reach the processor. The same 74AS280 IC used to generate parity also performs checking, making it a dual-role component in serial communication hardware.

Core Concept

A parity checker XORs together all received data bits plus the received parity bit. For even parity, if the total number of 1s in the complete received word is even, the XOR result is 0, meaning no error. If the result is 1, a single-bit error is flagged.

The checker includes the transmitted parity bit in its XOR chain. This is the key difference from the generator. The generator XORs only the data bits to produce P. The checker XORs data bits plus P and checks whether the result is 0.

The 74AS280 works as both generator and checker. In checker mode, all 9 inputs (8 data bits plus parity bit) connect to the IC. The even output goes low if an error occurs. Propagation delay is 8 ns. Supply is 5 V TTL. Power dissipation is 245 mW maximum.

Boolean Expression

The error flag for even parity checking is E = D₀ ⊕ D₁ ⊕ D₂ ⊕ D₃ ⊕ P. E = 0 means no error. E = 1 means a single-bit error. This expression is identical in form to the generator output, extended to include P. Two-bit errors produce E = 0 and go undetected. Parity is a single-error-detection code only.

Given:
Received 4-bit data + parity: D3 D2 D1 D0 P = 1 0 1 1 1
Original transmitted word had even parity.

Formula / Rule:
E = D3 XOR D2 XOR D1 XOR D0 XOR P

Step by step:
Step 1: D3 XOR D2 = 1 XOR 0 = 1
Step 2: 1 XOR D1  = 1 XOR 1 = 0
Step 3: 0 XOR D0  = 0 XOR 1 = 1
Step 4: 1 XOR P   = 1 XOR 1 = 0

Final Answer:
E = 0  → No error detected. Received word is valid.

Now suppose D0 flipped to 0 during transmission: D3 D2 D1 D0 P = 1 0 1 0 1
Step 1: 1 XOR 0 = 1
Step 2: 1 XOR 1 = 0
Step 3: 0 XOR 0 = 0
Step 4: 0 XOR 1 = 1
E = 1  → Error detected!

Exam Tip: VTU and Anna University questions frequently ask you to verify a received word for parity. Include the parity bit in your XOR chain — students who XOR only the data bits and compare against the received parity bit may get the same answer by coincidence, but the method is wrong and loses marks. Also remember: parity cannot detect 2-bit errors or correct any error. Error correction needs Hamming code.

Key Properties

• IC: 74AS280 (TTL), same device handles generation and checking
• Propagation delay: 8 ns typical at 5 V supply
• Fan-out: 20 TTL loads
• Power: 245 mW maximum for 74AS280
• Error detection: single-bit errors only; even number of errors go undetected
• Both even-parity-error and odd-parity-error outputs available simultaneously
• Cascade multiple ICs for data words wider than 9 bits

Quick Revision

• Checker XORs all received bits including the parity bit
• E = 0 means no error; E = 1 flags a single-bit error under even parity
• Two-bit errors produce E = 0 and are invisible to parity checking
• 74AS280 can be configured as generator or checker with pin connections
• Propagation delay 8 ns, supply 5 V, fan-out 20 (74AS280 TTL family)
• Parity detects errors but cannot locate or correct them
• For error correction, Hamming code or CRC is required
• Exam trap: XORing only data bits (not the received parity bit) is a wrong method even when it accidentally gives the right answer