Half Subtractor

A Half Subtractor is a combinational circuit that performs subtraction of two single binary bits and produces two outputs: the Difference (D) and the Borrow (B). It is the subtraction counterpart of the Half Adder, and understanding it builds the foundation for Full Subtractor design and multi-bit subtractor circuits.

Core Concept Explanation

When subtracting two binary bits, A minus B, there are four input combinations. When A is greater than or equal to B, the difference is computed directly. When A = 0 and B = 1, the result requires borrowing from the next higher bit position, analogous to borrowing in decimal subtraction. The Half Subtractor models exactly this single-bit operation.

The Difference output D represents the result of (A minus B minus 0), taking the least significant bit. The Borrow output indicates whether the current bit required a borrow from the adjacent higher-order bit. A borrow occurs only when A = 0 and B = 1, meaning we are subtracting a larger bit from a smaller one.

The Half Subtractor is called half because it has no Borrow-in input — it cannot accept a borrow generated by a previous bit position. This limitation is addressed by the Full Subtractor, which adds a third input for Borrow-in.

Mathematical Expression

The Boolean equations for the Half Subtractor outputs are derived directly from the truth table:

• Difference: D = A XOR B
• Borrow: B_out = A' AND B (NOT A, ANDed with B)

These two equations require three gates: one XOR for D, one NOT for A', and one AND for Borrow. The XOR gate correctly produces 1 when the bits differ, and the AND-NOT gate correctly identifies the only condition where borrowing is needed (A=0, B=1). Notably, D = A XOR B is identical to the sum expression in a Half Adder, but the borrow logic differs from carry logic.

Practical Understanding

The Half Subtractor forms the building block for the Full Subtractor, just as the Half Adder leads to the Full Adder. In practice, multi-bit subtractors are often implemented using adders with 2s complement representation, which converts subtraction into addition and avoids separate subtractor hardware. However, understanding the dedicated subtractor logic is fundamental for combinational circuit design and GATE examination.

In digital systems, a 1-bit comparator also uses similar logic to the Half Subtractor. The borrow output B_out = A'.B is equivalent to the condition A less than B for single bits, making it directly useful in comparison logic.

Given:
A = 0, B = 1 (subtract B from A for single bits)

Why this formula applies:
Half Subtractor equations apply for single-bit subtraction with no borrow-in.

Formula:
D = A XOR B
B_out = A' AND B

Substitution:
D = 0 XOR 1 = 1
A' = NOT 0 = 1
B_out = 1 AND 1 = 1

Calculation:
D = 1 (difference bit)
B_out = 1 (borrow required from next bit position)

Final Answer: D = 1, Borrow = 1 — meaning 0 - 1 = 1 with a borrow of 1 (equivalent to 10 - 1 = 1 in binary)

Exam Tip: In Half Subtractor, Borrow = A'B not AB'. A'B means borrow occurs when A=0 and B=1. A common trap is writing AB' (which is the condition A greater than B, meaning no borrow needed). Always verify from the truth table.

Quick Revision

• Half Subtractor subtracts two single bits A and B; produces Difference D and Borrow B_out.
• D = A XOR B (same gate as Half Adder sum).
• B_out = A' AND B — borrow occurs only when A=0, B=1.
• Gate count: 1 XOR + 1 NOT + 1 AND = 3 gates total.
• Half Subtractor has NO Borrow-in — cannot cascade directly; Full Subtractor adds Borrow-in.
• Exam trap: B_out = A'B, not AB'. AB' means A is larger than B — no borrow needed in that case.
• Truth table row A=1,B=1 gives D=0, B_out=0 — subtraction is exact, no borrow.