2-to-4 Decoder

Address decoding in 8085 microprocessor systems uses a 2-to-4 decoder to assert chip-select lines for four separate memory banks from just two address bits. The 74LS139 dual 2-to-4 decoder handles this in one IC.

Core Concept

A decoder converts an n-bit binary input into 2^n unique output lines. The 2-to-4 decoder maps each of the four input combinations (00, 01, 10, 11) to one of four outputs. Unlike a DEMUX, there is no separate data line—the output pattern depends solely on the address inputs.

The 74LS139 contains two independent 2-to-4 decoders. Outputs are active-low: the asserted output goes to logic 0 while others remain at 1. Propagation delay is 22 ns at 5 V. Fan-out is 20 standard TTL loads. Supply voltage: 4.75 V to 5.25 V.

Two 74LS139 decoders can be cascaded with one address bit used as an enable for each, yielding a 3-to-8 decoder. This cascading approach appears frequently in 8085 memory interface questions at Anna University.

Boolean Expression

Each output is a minterm of the two address inputs. Y0 = A1'·A0', Y1 = A1'·A0, Y2 = A1·A0', Y3 = A1·A0. For active-low outputs (74LS139): Y0_bar = NOT(A1'·A0') = A1 + A0 by De Morgan's law. Only one minterm evaluates to 1 at a time, so only one output is low at any given address.

Given:
  A1 = 1, A0 = 0, EN = 0 (enabled)

Formula:
  Y0 = A1'.A0'
  Y1 = A1'.A0
  Y2 = A1 .A0'
  Y3 = A1 .A0

Step by step:
  A1' = NOT(1) = 0
  A0' = NOT(0) = 1

  Y0 = 0 . 1 = 0  → active-low output = 1 (inactive)
  Y1 = 0 . 0 = 0  → active-low output = 1 (inactive)
  Y2 = 1 . 1 = 1  → active-low output = 0 (ACTIVE)
  Y3 = 1 . 0 = 0  → active-low output = 1 (inactive)

Final Answer:
  Y2 is asserted (logic 0 on active-low output)
  Address 10 (decimal 2) selects Y2

Exam Tip: The 74LS139 has active-low outputs. Questions that ask "which output is HIGH when A1A0=10" expect you to say none—Y2 goes LOW. Always check whether the question asks for active-high or active-low behavior. Anna University papers from 2018–2022 frequently test this distinction with the 74138/139 family.

Key Properties

• IC: 74LS139 (dual 2-to-4), 74HC139 (CMOS version, 2 V to 6 V)
• Outputs: active-low on 74LS139; invert externally for active-high
• Propagation delay: 22 ns (74LS139), 7 ns (74HC139)
• Fan-out: 20 standard TTL loads (LS family)
• Supply: 4.75–5.25 V (LS), 2–6 V (HC)
• Enable: active-low; when EN=1, all outputs are deasserted (held high)
• One IC decodes four unique binary addresses simultaneously

Quick Revision

• 2-to-4 decoder: 2 inputs → 4 outputs, one active at a time
• Each output = one minterm of the input variables
• 74LS139: active-low outputs, dual decoder in one 16-pin DIP
• No data input: output depends only on address, unlike DEMUX
• Used for chip select in memory interfacing, instruction decode in simple CPUs
• Cascade two 74LS139 to make 3-to-8 using one address bit as enable
• Exam trap: treating active-low outputs as active-high and answering that Y2=1 when A1A0=10