SIPO Shift Register

Serial-In Parallel-Out shift registers convert the serial bit stream from a UART or SPI bus into parallel data that a CPU data bus can read in a single cycle. They are inside every microcontroller's serial peripheral interface and every test-equipment logic analyzer input stage.

Core Concept

A Serial-In Parallel-Out (SIPO) shift register accepts one bit per clock on its serial input and presents all bits simultaneously on parallel output pins after N clock cycles. This is the fundamental serial-to-parallel conversion operation.

The 74LS164 is an 8-bit SIPO shift register in a DIP-14 package. It has two serial inputs (A and B) that are ANDed internally, an asynchronous active-low clear, and a common clock. Propagation delay clock-to-output is 18 ns. Maximum clock frequency is 36 MHz. Supply voltage is 5 V and power consumption is 80 mW.

The 74HC164 is the CMOS equivalent running from 2 V to 6 V at up to 70 MHz with under 1 mW static power. The 74HC595 adds an output storage register (latch) between the shift register and the output pins, preventing glitches on outputs while new data is being shifted in. The 74HC595 is the preferred IC in modern designs.

Boolean Expression

The operation of each stage is Q_k(t+1) = Q_(k-1)(t) for k > 0, and Q0(t+1) = SI(t). After N clock pulses, the register contains the last N bits that arrived at SI, with the most recently received bit in Q0 and the oldest in Q(N-1).

For the 74LS164 specifically, serial input = A AND B. Tying B HIGH makes A the effective serial input. Tying A LOW forces all zeros into the register regardless of B, acting as a software clear without using the CLR pin.

Given:
Load byte 0xB2 = 10110010 into a 74LS164 (8-bit SIPO).
MSB sent first. Trace Q0 through Q7 after each clock.
Initial state: all zeros. SI feeds Q0 (first FF).

Formula / Rule:
At each clock rising edge:
  Q7 <- Q6 <- Q5 <- Q4 <- Q3 <- Q2 <- Q1 <- Q0 <- SI
MSB of 0xB2 = 1, then 0, then 1, then 1, then 0, then 0, then 1, then 0.

Step by step (SI bit, then resulting Q0..Q7):
Clk 1: SI=1 => Q0=1, Q1..Q7=0       (1 0000000)
Clk 2: SI=0 => Q0=0, Q1=1, rest=0   (0 1000000)
Clk 3: SI=1 => Q0=1, Q1=0, Q2=1    (1 0100000)
Clk 4: SI=1 => Q0=1, Q1=1, Q2=0, Q3=1 (1 1010000)
Clk 5: SI=0 => Q0=0, Q1=1, Q2=1, Q3=0, Q4=1 (0 1101000)
Clk 6: SI=0 => Q0=0, Q1=0, Q2=1, Q3=1, Q4=0, Q5=1 (0 0110100)
Clk 7: SI=1 => Q0=1, Q1=0, Q2=0, Q3=1, Q4=1, Q5=0, Q6=1 (1 0011010)
Clk 8: SI=0 => Q0=0, Q1=1, Q2=0, Q3=0, Q4=1, Q5=1, Q6=0, Q7=1
       Q7..Q0 = 1 0 1 1 0 0 1 0 = 10110010 = 0xB2

Final Answer:
After 8 clocks, Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 = 10110010.
Parallel byte 0xB2 is now available on all 8 output pins simultaneously.

Exam Tip: SIPO is serial-to-parallel conversion; PISO is parallel-to-serial. Students often swap these. In GATE, if you are asked which register type is used inside a UART transmitter, the answer is PISO (converts parallel CPU data to serial stream). The UART receiver uses SIPO. Also note that the 74HC595 has an extra latch (storage register) not present in the 74LS164 — the latch prevents output glitches during shifting.

Key Properties

• 74LS164: 8-bit SIPO, 36 MHz, 18 ns propagation delay, 5 V, 80 mW
• 74HC164: CMOS, 70 MHz, 2–6 V supply, under 1 mW static power
• 74HC595: adds output latch to prevent glitches; preferred in production designs
• Serial input of 74LS164 is AND of pins A and B; tie B HIGH for normal operation
• Asynchronous CLR_bar pin clears all stages instantly, independent of clock
• N bits require N clock cycles to load — that is the serial transmission time
• Output data is available in parallel on all Q pins simultaneously after N clocks

Quick Revision

• SIPO: one serial input, N parallel outputs, needs N clocks to load N bits
• Each stage: Q_k(t+1) = Q_(k-1)(t); Q0(t+1) = SI(t)
• 74LS164 serial input = A AND B; tie B=1 for normal serial input on A
• 74HC595 adds output latch register to prevent output glitches during shift
• MSB-first or LSB-first is a convention choice; hardware does not enforce either
• UART receiver uses SIPO; UART transmitter uses PISO — opposite roles
• Clock frequency limit determines maximum baud rate in serial interfaces
• Exam trap: Stating that the 74LS164 has an output latch — it does not; the 74HC595 does. Confusing the two costs marks on IC-specific questions