DRAM

DRAM is the main memory in every PC, laptop, and smartphone. A 16 GB DDR5 DIMM packs billions of single-transistor cells onto a chip smaller than a fingernail, making it the densest mainstream semiconductor memory ever built.

Core Concept

Dynamic RAM (DRAM) stores each bit as charge on a small capacitor (approximately 30 fF) controlled by a single access transistor. This 1T1C cell is far smaller than the 6T SRAM cell, enabling much higher density. But the capacitor leaks charge through the transistor subthreshold current and dielectric leakage. After approximately 64 ms, the stored charge becomes indistinguishable from zero. To retain data, every row must be read and rewritten within this window — this is the refresh operation.

The classic 4164 DRAM is a 64K×1 device (one bit per address). It has only 8 address pins (A0–A7) despite needing a 16-bit address (65,536 locations). This is achieved by address multiplexing: the 16-bit address is sent in two 8-bit halves. The row address is latched when RAS (Row Address Strobe) goes LOW. Then the column address is placed on the same pins and latched when CAS (Column Address Strobe) goes LOW. This halves the pin count at the cost of a two-phase addressing protocol.

Reading DRAM is destructive: the charge on the capacitor partially transfers to the bitline during sense amplification, partially collapsing the stored voltage. The sense amplifier detects the tiny voltage change on the bitline, amplifies it, and then drives it back into the cell to restore the full charge. Modern SDRAM (synchronous DRAM) and DDR variants still use the same 1T1C cell but add a synchronous burst interface, on-chip refresh controllers, and internal row buffers for page-mode access.

Boolean Expression

DRAM capacity uses the same formula: capacity = 2^(row bits + column bits) × data width. For the 4164 with 8-bit multiplexed address: row address = 8 bits (256 rows), column address = 8 bits (256 columns), total = 256×256 = 65,536 = 64K locations, data width = 1 bit. Total = 64 Kbits. The 41256 extends to 256K×1 using 9-bit multiplexed addresses. For multi-bit-wide DRAMs, multiply: four 4164 chips in parallel give 64K×4.

Given:
DRAM chip: 4164 (64K × 1 bit)
Address pins: 8 (A0–A7), multiplexed row/column
Calculate refresh requirements and full-system memory

Formula / Rule:
Total addresses = 2^(row_bits + col_bits)
Refresh: all rows in 64 ms
System memory width = number of chips in parallel

Step by step:
Row address: 8 bits → 2^8 = 256 rows
Column address: 8 bits → 2^8 = 256 columns
Total locations: 256 × 256 = 65,536 = 64K
Data width per chip: 1 bit

Refresh calculation:
256 rows must be refreshed in 64 ms
Refresh interval = 64 ms / 256 = 250 µs per row
(one RAS-only cycle every 250 µs is sufficient)

Building 64KB × 8 system from 4164 chips:
8 chips in parallel (each provides 1 bit of the 8-bit data bus)
64KB × 8 = 512 Kbits total, using 8 × 4164 chips

Final Answer:
4164: 8 address pins, 256 rows, 250 µs refresh interval
8 chips → 64KB system memory (8-bit data bus)

Exam Tip: GATE frequently tests RAS/CAS multiplexing and refresh period calculations. Key numbers: 4116 = 16K×1 (7 address pins, 128 rows), 4164 = 64K×1 (8 pins, 256 rows), 41256 = 256K×1 (9 pins, 512 rows). Refresh period = 64 ms / (number of rows). A common trap is assuming DRAM reads are non-destructive — they are destructive. The sense amplifier restores the charge as part of every read cycle. Also note: DRAM is volatile and slower than SRAM, but much cheaper per bit.

Key Properties

• Cell structure: 1 NMOS transistor + 1 capacitor (~30 fF) per bit — highest density mainstream memory
• 4164: 64K×1, 8 address pins (multiplexed RAS/CAS), VCC=5V, tACC≈150 ns, 16-pin DIP
• Refresh required: all rows within 64 ms — typical interval = 64 ms / number of rows
• Read is destructive: sense amplifier must restore cell charge after every read operation
• Address multiplexing: row address on RAS↓, column address on CAS↓ — halves pin count
• DRAM cell area ~6 F² vs SRAM 50–100 F² — 8–16× higher density enables affordable GB-scale memory
• DDR5 SDRAM: same 1T1C cell, synchronous burst interface, 4800–8400 MT/s, 1.1V supply

Quick Revision

• DRAM = 1 transistor + 1 capacitor per cell — simpler than 6T SRAM but needs refresh
• Capacitor charge leaks in ~64 ms → periodic refresh of every row is mandatory
• Address multiplexing: same pins carry row address (latched by RAS) then column (latched by CAS)
• Read is destructive — sense amplifier restores charge as part of every read
• 4116 = 16K×1 (7-pin addr), 4164 = 64K×1 (8-pin), 41256 = 256K×1 (9-pin)
• Refresh interval = 64 ms / number of rows (e.g. 4164: 64 ms / 256 rows = 250 µs)
• DRAM is volatile, slower (150 ns+) and cheaper per bit than SRAM (sub-10 ns)
• Exam trap: saying DRAM read is non-destructive — it is always destructive; the sense amp write-back is automatic but not free