FPGA vs ASIC

Every new SoC design team faces the same decision: spend six months taping out a custom ASIC or ship next quarter with an FPGA. That choice determines NRE cost, unit cost, performance, and power for the lifetime of the product.

Core Concept

An ASIC (Application-Specific Integrated Circuit) is a chip designed and fabricated for exactly one function. Every transistor is hand-placed (custom) or synthesized from standard cells and routed by EDA tools on a specific process node (e.g., TSMC 7 nm). The result is the most area- and power-efficient implementation possible, but the masks cost $1-10 million and take 12-24 months from RTL to silicon.

An FPGA implements the same function in a sea of LUTs and routing. The overhead of the configuration SRAM, routing multiplexers, and general-purpose structure means an FPGA uses 10-100× more power and 10-40× more area than an equivalent ASIC. The Xilinx UltraScale+ VU13P is the largest commercially available FPGA with 3.78 million LUTs and 260 BRAM tiles, yet a custom ASIC could implement the same function on a die one-tenth the size.

The crossover volume is roughly 100,000 units. Below that, FPGA NRE savings outweigh the higher per-unit cost. Above that, ASIC unit economics win. Modern eFPGA (embedded FPGA) IP cores allow designers to include a small programmable fabric inside an ASIC, getting field-update capability in a mixed strategy.

Boolean Expression

For any RTL description, the same Verilog/VHDL synthesizes to both targets. FPGA synthesis maps to LUTs; ASIC synthesis maps to standard cells (NAND, NOR, DFF from a PDK library). The timing constraint Fmax = 1 / (critical_path_delay) limits clock frequency in both. ASIC critical paths are shorter because standard cell gates have ~0.05 ns delay at 7 nm versus ~0.5 ns for an LUT at 16 nm FPGA process.

Given:
  Design: 16-bit multiplier
  FPGA: Xilinx Artix-7 XC7A100T (28 nm equivalent FPGA process)
  ASIC: TSMC 28 nm HPC standard cell library

Formula / Rule:
  FPGA uses DSP48 hard blocks for multiply
  ASIC synthesis uses Wallace tree multiplier from standard cells

Step by step (comparison):
  FPGA:
    DSP48E1 block: 18×18 signed multiply in 1 clock cycle
    Fmax: up to 450 MHz with registered output
    Power: DSP48 block ~20 mW per multiplier at 250 MHz
    Area: 1 DSP48 slice (hard block, not LUT area)

  ASIC (TSMC 28 nm):
    Wallace tree 16×16: ~1200 standard cells
    Fmax: ~1.5 GHz at 0.9 V
    Power: ~2 mW at 500 MHz
    Area: ~0.01 mm² at 28 nm

Final Answer:
  ASIC is 10× faster, ~10× lower power for same function.
  FPGA advantage: zero NRE, field-upgradeable, available in weeks.
  ASIC break-even volume at $2M NRE and $5 unit savings: 400,000 units.

Exam Tip: GATE questions on FPGA vs ASIC test three concepts: (1) NRE vs unit cost trade-off and break-even volume. (2) FPGA is reprogrammable; ASIC is not. (3) FPGA uses SRAM LUTs (configurable); ASIC uses fixed standard cells or custom transistors. Do not confuse 'time to market' (FPGA wins) with 'long-term production cost' (ASIC wins). Structured ASIC is a middle ground — pre-diffused base layers, only metal layers customized — reducing mask cost to ~$500K.

Key Properties

• FPGA NRE: ~$0 for dev board; ASIC NRE: $1-10 M at 28 nm, $30-100 M at 7 nm (mask sets)
• FPGA unit cost: Xilinx XC7A100T ~$30 qty 1K; ASIC unit cost: $0.50-$5 at 100K+ volume
• Performance gap: ASIC 1-5 GHz vs FPGA 100-500 MHz for same function at same process node
• Power gap: FPGA 10-100× more power than ASIC for equivalent logic — routing SRAM is always switching
• FPGA reprogrammable in the field: firmware updates possible without hardware change
• ASIC time to market: 12-24 months from RTL sign-off; FPGA: 2-8 weeks from RTL to working board
• eFPGA: embedded FPGA fabric inside an ASIC (e.g., Flex Logix EFLX) — combines both approaches

Quick Revision

• FPGA wins: low volume, fast time-to-market, field upgrade, prototyping, algorithm exploration
• ASIC wins: high volume (>100K units), performance, power, area, IP protection
• FPGA uses SRAM LUTs (10-40× more area than ASIC for same function)
• ASIC uses standard cells or custom transistors — no reconfiguration overhead
• Structured ASIC: middle ground — lower NRE than full-custom, higher performance than FPGA
• Both compile from the same Verilog/VHDL RTL — synthesis tool targets differ (LUT map vs cell library)
• Exam trap: students say 'FPGA is always better for prototyping ASICs' — true for logic verification, but FPGA cannot replicate analog, RF, or sub-ns timing behavior of the final ASIC