Gated SR Latch

The gated SR latch adds a single control input that synchronizes when the latch responds to S and R — turning an asynchronous circuit into a level-sensitive one. Every microcontroller GPIO latch and bus transceiver uses this principle to control data flow.

Core Concept

A gated SR latch (also called a clocked SR latch or level-sensitive SR latch) adds an Enable (EN) input to the basic SR latch. When EN=0, the S and R inputs are blocked by AND gates — the latch holds its state regardless of S and R changes. When EN=1, the latch is transparent and behaves exactly like an ordinary SR latch.

The circuit adds two AND gates in front of the NOR latch core. The AND gates compute (S AND EN) and (R AND EN). This means S and R are only passed through when EN is high. The 74HC279 quad SR latch IC implements active-LOW S' and R' inputs with 4.5 ns propagation delay at 5 V and a fan-out of 50 CMOS loads.

The term transparent latch describes this behavior: while EN=1, output Q tracks input S immediately. The latch becomes opaque (holds) when EN falls. This is level-sensitive, not edge-triggered — any glitch on S or R during EN=1 can affect Q. This is the key difference between a gated latch and a flip-flop.

Boolean Expression

The effective inputs to the NOR core are S_eff = S AND EN and R_eff = R AND EN. The characteristic equation becomes: Q(next) = S·EN + (R·EN)'·Q = S·EN + (R'+EN')·Q. When EN=0 this reduces to Q(next) = Q (hold). When EN=1 it reduces to Q(next) = S + R'Q, the normal SR latch equation. The forbidden condition when EN=1 is still S=R=1.

Given:
  Gated SR latch, Q=0 initially
  Input sequence:
    t1: EN=0, S=1, R=0
    t2: EN=1, S=1, R=0
    t3: EN=1, S=0, R=0
    t4: EN=1, S=0, R=1
    t5: EN=0, S=1, R=0

Formula / Rule:
  EN=0 → Q(next) = Q (hold, S and R ignored)
  EN=1 → Q(next) = S + R'·Q (normal SR behavior)

Step by step:
  t1: EN=0 → hold → Q remains 0
  t2: EN=1, S=1, R=0 → Set → Q = 1
  t3: EN=1, S=0, R=0 → Hold → Q = 1
  t4: EN=1, S=0, R=1 → Reset → Q = 0
  t5: EN=0, S=1 → hold → Q remains 0 (S ignored)

Final Answer:
  Q sequence: 0, 0, 1, 1, 0, 0
  EN=0 at t1 and t5 blocks input changes.

Exam Tip: The most tested concept is the difference between a gated latch and an edge-triggered flip-flop. A gated latch is transparent (tracks input) during the entire HIGH level of EN. An edge-triggered flip-flop only samples input at the clock edge. Glitches during EN=1 propagate through the latch but not through an edge-triggered flip-flop. GATE questions often describe a timing diagram and ask which circuit type is shown — look for whether the output changes continuously during the clock high phase (latch) or only at the edge (flip-flop).

Key Properties

• EN=0: latch holds state; S and R inputs have no effect.
• EN=1: latch is transparent; Q follows S/R immediately (level-sensitive).
• Forbidden condition: S=R=1 when EN=1 (same as basic NOR latch).
• 74HC279: quad SR latch, 4.5 ns propagation delay, 5 V supply, 50 CMOS fan-out.
• Transparent latch vs. flip-flop: latch tracks input during full EN pulse; flip-flop samples only at edge.
• Glitches on S or R during EN=1 directly affect Q — no noise immunity during high enable.
• Used in bus transceivers, address latches (74HC373), and GPIO output registers.

Quick Revision

• Gated SR latch = SR latch + AND gate steering controlled by EN.
• EN=0 → hold (opaque); EN=1 → transparent (tracks inputs).
• Characteristic: Q(next) = S·EN + (R'+EN')·Q.
• Forbidden: S=R=1 with EN=1; same constraint as basic SR latch.
• 74HC279 quad latch IC: 4.5 ns, 5 V, active-LOW S' and R'.
• Level-sensitive not edge-triggered — key distinction from D flip-flop.
• 74HC373 octal transparent latch uses this principle for bus address latching.
• Exam trap: saying a latch 'clocks' data on the rising edge — latches respond to the full level of EN, not just the transition.