Priority Encoder

Keyboard controllers and interrupt arbitration circuits use a priority encoder to compress multiple simultaneous active inputs into a single binary output representing the highest-priority input. The 74HC148 encodes eight inputs into a 3-bit binary code in under 24 ns.

Core Concept

A priority encoder differs from a plain encoder by handling multiple simultaneous active inputs gracefully. When more than one input is asserted, the output reflects only the highest-priority input. Priority is assigned by position: higher index means higher priority in the 74HC148 (I7 beats I6 beats I5, and so on).

The 74HC148 has eight active-low inputs and three active-low outputs. It also provides GS (Group Select, active-low), which goes low when any input is active, and EO (Enable Output, active-low), which goes low when the chip is enabled but no input is active. These two pins allow cascading multiple 74HC148 ICs for 16-to-4 or larger encoders.

Propagation delay is 24 ns at 5 V. Supply voltage: 2 V to 6 V. Fan-out: 10 HC loads. The TTL equivalent is 74LS148 with a 25 ns delay. In microprocessor interrupt controllers like the 8259A, a similar priority resolution scheme governs IRQ0–IRQ7.

Boolean Expression

Output bits for the active-high equivalent (before inversion): A2 = I4 + I5 + I6 + I7. A1 = I2 + I3 + I6 + I7 (with I4, I5, I6, I7 masking lower inputs). A0 = I1 + I3 + I5 + I7 (similarly masked). The masking ensures that if I7 is active, lower-index inputs are ignored regardless of their state. On the actual 74HC148, all signals are active-low, so complement each expression.

Given:
  Active-low inputs: I7=1, I6=1, I5=0, I4=1, I3=1, I2=1, I1=1, I0=1
  (Active-low: 0 = asserted. So I5 is the only asserted input.)
  EI = 0 (enable input, active-low, chip is enabled)

Priority rule:
  Highest asserted input wins.
  I5 is asserted (0). No higher input (I6, I7) is asserted.
  Encoded value = 5 (binary 101)

Active-low output calculation:
  A2_bar = NOT(bit2 of 5) = NOT(1) = 0
  A1_bar = NOT(bit1 of 5) = NOT(0) = 1
  A0_bar = NOT(bit0 of 5) = NOT(1) = 0

  GS_bar = 0 (at least one input active)
  EO_bar = 1 (chip is enabled and input is active)

Final Answer:
  Outputs A2_bar A1_bar A0_bar = 0 1 0
  Decoded active-high = 101 = 5 (I5 selected)

Exam Tip: Priority encoders have a valid output flag GS. When no input is active, GS=1 (inactive) and the output code is meaningless—do not interpret it as a valid address. VTU and Anna University questions often include "all inputs inactive" scenarios and expect you to state that GS indicates invalid output. Also, cascading two 74HC148 chips: connect EO of the high-priority chip to EI of the low-priority chip.

Key Properties

• IC: 74HC148 (8-to-3), 74LS148 (TTL, 25 ns), CD4532B (CMOS 8-input)
• Priority: highest-index active input wins; lower inputs ignored
• Inputs and outputs: all active-low on 74HC148
• GS output: active-low, indicates at least one input is asserted
• EO output: active-low when chip enabled but no input active (cascade use)
• Propagation delay: 24 ns (74HC148 at 5 V)
• Supply: 2 V to 6 V (HC CMOS); fan-out 10 HC loads

Quick Revision

• Priority encoder: multiple active inputs allowed; only highest wins
• 74HC148: 8 active-low inputs, 3-bit active-low output + GS + EO
• GS=0 means valid encoded output is present
• EO=0 means chip enabled but all inputs inactive
• Cascade: EO of chip 1 (high priority) → EI of chip 2 (low priority)
• Used in 8259A PIC, keyboard scan controllers, interrupt arbiters
• Exam trap: reading the 3-bit output when GS=1 (no valid input) and treating it as a real encoded address