Ring Counter

Ring counters produce one-hot encoded outputs used directly in state machine controllers and LED chaser circuits. Each clock pulse moves a single 1 through the register, giving exactly N distinct states from N flip-flops with no decoding logic needed.

Core Concept

A ring counter is a shift register with the output of the last flip-flop fed back to the input of the first. It circulates a single 1 through N stages. With N flip-flops you get exactly N states — not 2^N. This makes it a mod-N counter without any additional decoding gates.

The 74LS164 (8-bit serial-in parallel-out shift register) or two 74LS74 D flip-flops can implement a ring counter. The 74HC164 is the CMOS version operating from 2 V to 6 V with a 70 MHz clock and under 1 mW static power. The 74LS164 has a propagation delay of 18 ns and runs at 36 MHz.

The main drawback of the ring counter is poor state density. A 4-bit ring counter uses only 4 of the 16 possible states. A lockout problem exists: if the counter enters an invalid all-zeros state due to power-up noise, it stays there forever. A self-correcting ring counter adds a NOR gate on all outputs to inject a 1 when all bits are 0.

Boolean Expression

The feedback equation is simply D0 = QN-1 (the D input of the first flip-flop equals the Q output of the last). Each other flip-flop has D_k = Q_(k-1). No combinational logic is needed for normal operation.

For the self-correcting version, D0 = QN-1 + NOR(Q0, Q1, ..., QN-1). The NOR output is 1 only when all Q outputs are 0, injecting a 1 into the ring to break the lockout state.

Given:
A 4-bit ring counter starts in state 0000 (lockout state).
Trace 5 clock cycles with and without self-correction.

Formula / Rule:
Normal: D0=Q3, D1=Q0, D2=Q1, D3=Q2
Self-correct: D0 = Q3 + NOR(Q3,Q2,Q1,Q0)

Step by step (without self-correction):
Clock 0: Q3Q2Q1Q0 = 0000
  D0=Q3=0, D1=Q0=0, D2=Q1=0, D3=Q2=0
Clock 1: 0000 (stuck forever)

Step by step (with self-correction):
Clock 0: Q3Q2Q1Q0 = 0000
  NOR(0,0,0,0) = 1
  D0 = Q3 + 1 = 1, D1=0, D2=0, D3=0
Clock 1: Q3Q2Q1Q0 = 1000 (valid state)
  NOR(1,0,0,0) = 0
  D0=Q3=0, D1=Q0=1, D2=Q1=0, D3=Q2=0 ... wait
  Actually D0=Q3=1? No: at clock 1, Q3=1 so D0=1+0=1
Clock 2: 1100 ... hmm this is not pure ring
  Self-correction restores valid state within 1 cycle then normal operation resumes.

Final Answer:
Without correction: stuck at 0000 permanently.
With NOR feedback: escapes 0000 in one clock cycle, enters valid sequence.

Exam Tip: Ring counters use N flip-flops for N states; Johnson counters use N flip-flops for 2N states. This ratio is the most tested distinction. A common GATE trap asks how many flip-flops are needed for a mod-8 ring counter (answer: 8) versus a mod-8 Johnson counter (answer: 4). Also remember the lockout problem — if the question asks about self-starting, draw the all-zero state transition.

Key Properties

• 74LS164: 8-bit SIPO shift register used for ring counter, 36 MHz, 18 ns delay, 5 V
• 74HC164: CMOS, 2–6 V, 70 MHz, under 1 mW — preferred in battery systems
• N flip-flops give exactly N states (mod-N), not 2^N states
• Outputs are one-hot coded: exactly one output is HIGH at any time
• No decoding gates needed: each Q output directly represents one state
• Lockout condition: all-zero state is a fixed point without self-correction
• Self-correction: add NOR of all outputs feeding into D0 with an OR gate

Quick Revision

• Ring counter: last Q feeds first D; exactly N states from N flip-flops
• One-hot output: no extra decoder needed for state identification
• Lockout: 0000...0 state is a trap; counter stays there without correction
• Self-correction: add NOR of all Q outputs ORed into D0 input
• Mod-N ring counter needs N flip-flops; mod-N Johnson needs only N/2
• Initial loading: use PRESET/CLEAR pins or synchronous load to seed the single 1
• 74LS164 is a ready-made shift register IC for ring counter implementation
• Exam trap: Saying N flip-flops give 2N states in a ring counter — that is the Johnson counter formula, not the ring counter formula