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Carry Lookahead Adder

Generate and propagate, fast carry computation, CLA.

Darshan N
Updated: 7 April 2026
11 min read

A 32-bit processor cannot wait 32 ripple carry delays every time it adds two numbers. The carry lookahead adder solves this by computing all carry signals in parallel, cutting addition time from O(n) to O(log n) gate delays.

4-bit Carry Lookahead Adder (CLA) — 74182 / 74283Bit 0 FABit 1 FABit 2 FABit 3 FACLA Logic74182G, P inputsC1,C2,C3 outG0,P0 … G3,P3 fed simultaneously to 74182 CLA unitGenerate / Propagate Logic:Gi = Ai AND Bi (carry generated at bit i regardless of cin)Pi = Ai XOR Bi (carry propagated from bit i-1)C1 = G0 + P0·C0C2 = G1 + P1·G0 + P1·P0·C0C3 = G2 + P2·G1 + P2·P1·G0 + P2·P1·P0·C0ICs: 74283 (4-bit CLA), 74182 (CLA unit)
Figure 1: 4-bit CLA structure using 74182 lookahead carry unit and 74283 adder IC

Core Concept

A carry lookahead adder (CLA) eliminates the serial carry chain of a ripple carry adder (RCA). In an RCA, bit n cannot start until bit n-1 finishes, so delay grows linearly. A CLA pre-computes every carry in parallel using only the original inputs.

Two auxiliary signals are defined for each bit position i. The generate signal Gi = Ai AND Bi means bit i will produce a carry regardless of the incoming carry. The propagate signal Pi = Ai XOR Bi means bit i will pass along any incoming carry. All Gi and Pi values are computed simultaneously in one gate delay.

The 74283 is a real 4-bit CLA IC in TTL logic. It operates from 5 V, has a propagation delay of about 17 ns (worst case), and a fan-out of 10 in TTL. The companion 74182 look-ahead carry unit lets you cascade multiple 74283 chips for 8-bit or 16-bit addition without reverting to ripple carry between groups.

Boolean Expression

The carry equations are Ci+1 = Gi + Pi · Ci. Expanding recursively: C1 = G0 + P0·C0; C2 = G1 + P1·G0 + P1·P0·C0; C3 = G2 + P2·G1 + P2·P1·G0 + P2·P1·P0·C0. Each carry depends only on the original A, B inputs and C0, so all three carry bits are available after the same gate depth regardless of word width.

Example
Given:
  A = 1011 (11), B = 0110 (6), C0 = 0
  Add using CLA: find C1, C2, C3, C4 and Sum

Formula / Rule:
  Gi = Ai AND Bi
  Pi = Ai XOR Bi
  Ci+1 = Gi + Pi·Ci

Step by step:
  Bit positions (i=0 is LSB):
  i=0: A0=1, B0=1  G0=1, P0=0
  i=1: A1=1, B1=1  G1=1, P1=0
  i=2: A2=0, B2=1  G2=0, P2=1
  i=3: A3=1, B3=0  G3=0, P3=1

  C1 = G0 + P0·C0 = 1 + 0·0 = 1
  C2 = G1 + P1·C1 = 1 + 0·1 = 1
  C3 = G2 + P2·C2 = 0 + 1·1 = 1
  C4 = G3 + P3·C3 = 0 + 1·1 = 1  (carry out)

  Sum bit Si = Pi XOR Ci:
  S0 = P0 XOR C0 = 0 XOR 0 = 0
  S1 = P1 XOR C1 = 0 XOR 1 = 1  (wait — Pi=Ai XOR Bi)
    (re-check: P0=1 XOR 1=0, P1=1 XOR 1=0)
  S0 = 0 XOR 0 = 0
  S1 = 0 XOR 1 = 1  wait, Si = Pi XOR Ci
  S0 = P0 XOR C0 = 0 XOR 0 = 0
  S1 = P1 XOR C1 = 0 XOR 1 = 1
  S2 = P2 XOR C2 = 1 XOR 1 = 0
  S3 = P3 XOR C3 = 1 XOR 1 = 0

  Sum = C4 S3 S2 S1 S0 = 1 0 0 1 0 = 10001

Final Answer:
  11 + 6 = 17 = 10001 in binary  ✓
  Carry-out C4 = 1 (5-bit result)
Exam Tip: GATE problems on CLA ask for the number of gate delays to compute carry Cn. In a 4-bit CLA, all carries are ready in 2 gate delays (one for G/P, one for the carry equation). Compare this to a 4-bit RCA which needs 2n = 8 gate delays. For a two-level CLA (e.g., 16-bit using four 4-bit groups with a 74182), the total delay is 4 gate levels, not 16. Always count the generate/propagate computation as the first level.

Key Properties

  • 74283: 4-bit CLA adder, 5 V TTL, propagation delay 17 ns (typ 12 ns), fan-out 10.
  • 74182: look-ahead carry unit, generates group carry G and propagate P for cascading.
  • Delay is O(log n) with two-level lookahead vs O(n) for ripple carry.
  • Gate count is higher than RCA — each carry equation adds AND-OR logic — but speed justifies the cost.
  • Power dissipation: 74283 draws about 80 mA from 5 V supply (400 mW max).
  • CMOS equivalent 74HC283 operates from 2 V to 6 V with much lower static power.
  • Two-level CLA (four 4-bit groups + 74182) adds 16 bits in only 4 gate delays.

Quick Revision

  • Gi = Ai AND Bi (generate); Pi = Ai XOR Bi (propagate).
  • All G and P computed in one gate delay simultaneously.
  • Carry equations expand in terms of G, P, C0 only — no serial dependency.
  • 4-bit CLA: 2 gate delays for carry, 3 for sum.
  • 74283 is the standard 4-bit CLA IC; 74182 extends it.
  • RCA delay = 2n gate delays; CLA delay = 2 log2(n) gate delays.
  • Sum Si = Pi XOR Ci (one more gate delay after carry available).
  • Exam trap: confusing the propagate signal Pi = Ai XOR Bi with the carry generate Gi = Ai AND Bi — they look similar but serve completely different roles; P is for the sum bit and carry forwarding, G is for independent carry creation.

Carry Lookahead Quiz

Test your understanding of generate, propagate, and CLA carry computation logic.

Question 1 of 3

Q1.In a carry lookahead adder, the generate term G_i for stage i is defined as: