Modeling Adders

Adders are the most fundamental arithmetic circuits in digital design. Starting from the simple half adder and building up to the ripple carry adder, modeling these circuits in Verilog teaches both the logic structure and the hierarchical design methodology. Understanding adder timing and carry propagation is also directly relevant to GATE questions on propagation delay.

Core Concept: Half Adder, Full Adder, and Carry Propagation

A half adder adds two single-bit binary inputs A and B and produces a Sum and a Carry output. It is called a half adder because it cannot accommodate a carry input from a previous stage. The logic equations are direct: Sum = A XOR B and Carry = A AND B. While simple, the half adder is insufficient for multi-bit addition since intermediate bits require three inputs.

A full adder extends the half adder by accepting a carry-in (Cin) in addition to the two operand bits. This allows full adders to be chained together for multi-bit addition. The sum equation becomes Sum = A XOR B XOR Cin. The carry out is produced when at least two of the three inputs are HIGH, making it a majority function: Cout = (A AND B) OR (B AND Cin) OR (A AND Cin).

A ripple carry adder (RCA) is constructed by cascading n full adders where the carry output of each stage is connected to the carry input of the next. The carry starts at zero for the LSB stage and ripples through each bit position. The critical path delay is linear in n since the carry must propagate through all n stages before the final sum and carry out are valid.

Mathematical Expression

For a full adder, the Boolean expressions are: Sum = A XOR B XOR Cin and Cout = AB + BCin + ACin. The carry out expression can also be written as Cout = (A XOR B) AND Cin OR (A AND B), which is the form used when implementing a full adder from two half adders and an OR gate.

For an n-bit ripple carry adder, the worst-case propagation delay is t_total = n * t_FA where t_FA is the delay of one full adder. This O(n) delay makes the RCA unsuitable for wide operands in high-speed designs, motivating faster architectures such as carry lookahead adders (CLA) which compute carry signals in O(log n) time using generate and propagate functions.

Verilog Modeling Approaches

In Verilog, the half adder can be modeled with dataflow assigns: assign sum = a ^ b; and assign carry = a & b;. The full adder adds the carry-in: assign sum = a ^ b ^ cin; and assign cout = (a & b) | (b & cin) | (a & cin);. The most concise behavioral model uses Verilog arithmetic directly with bit concatenation: assign {cout, sum} = a + b + cin; which captures both the sum and carry in one statement.

For a 4-bit ripple carry adder, the structural modeling approach instantiates four full adder modules and connects the carry chain explicitly. This is an important exam topic because structural models use module instantiation with named or positional port connections. The alternative behavioral model simply writes assign {cout, sum} = a + b; for the entire 4-bit operands, leaving the carry chain implementation to the synthesis tool.

Given:
A = 4b0111 (decimal 7), B = 4b0101 (decimal 5), Cin = 0

Why this formula applies:
4-bit ripple carry adder adds two 4-bit numbers bit by bit.
Carry ripples from bit 0 to bit 3.

Formula:
{Cout, Sum[3:0]} = A + B + Cin
Each bit: S[i] = A[i] XOR B[i] XOR C[i]; C[i+1] = majority(A[i],B[i],C[i])

Substitution:
Bit 0: A=1,B=1,Cin=0 → S=0, C1=1
Bit 1: A=1,B=0,C1=1 → S=0, C2=1
Bit 2: A=1,B=1,C2=1 → S=1, C3=1
Bit 3: A=0,B=0,C3=1 → S=1, C4=0

Calculation:
  0111 (7)
+ 0101 (5)
------
  1100 (12)

Final Answer:
Sum = 4b1100 (decimal 12), Cout = 0
No carry out since 7+5=12 fits in 4 bits.

Exam Tip: For GATE, the worst-case propagation delay of an n-bit ripple carry adder is 2n gate delays if each full adder has 2 gate levels. For a 4-bit RCA, delay = 8 gate delays. The carry lookahead adder reduces this to O(log n). Also, in Verilog, assign {cout, sum} = a + b; is only correct when a and b are treated as unsigned; for signed addition, use $signed() casting.

• Half adder: Sum = A XOR B, Carry = A AND B. Two inputs only, no carry-in.
• Full adder: Sum = A XOR B XOR Cin, Cout = (A AND B) OR (B AND Cin) OR (A AND Cin).
• Ripple carry adder chains n full adders; Cout[i] connects to Cin[i+1].
• Verilog one-liner: assign {cout, sum} = a + b + cin; models a full adder behaviorally.
• RCA worst-case delay = n * t_FA; O(n) delay is a scalability bottleneck.
• Structural model of RCA requires explicit full adder module instantiation with named port connections.

Quick Revision

• Half adder: 2 inputs, 2 outputs (Sum, Carry); no carry-in capability.
• Full adder: 3 inputs (A, B, Cin), 2 outputs; Sum = A XOR B XOR Cin.
• Cout formula: AB + BCin + ACin (majority function).
• 4-bit RCA: 4 full adders; worst-case delay = 4 * t_FA = 8 gate levels if each FA is 2 levels.
• Behavioral Verilog: assign {cout, sum} = a + b + cin; works for any bit width.
• Exam trap: Using 4-bit result reg for two 4-bit inputs discards carry. Use {cout, sum} with correct widths.
• CLA reduces delay to O(log n) using generate (G=AB) and propagate (P=A XOR B) signals.