Switch Level Modeling

At the lowest abstraction level in Verilog, digital circuits can be described using individual transistor-level switches. Switch-level modeling uses built-in Verilog primitives that represent NMOS and PMOS transistors as controllable switches, enabling accurate circuit-level descriptions without a separate analog simulator. This level of modeling is important for understanding CMOS circuit behavior in Verilog and is tested in GATE for understanding signal strength and transistor-level design.

Core Concept Explanation

Switch-level modeling uses four basic unidirectional switch primitives: nmos and pmos (which pass signals in one direction only), and their resistive versions rnmos and rpmos (which weaken signal strength during passing). The nmos switch conducts when its gate input is logic 1, while the pmos switch conducts when its gate input is logic 0, exactly mirroring real transistor behavior.

For the bidirectional transmission gate, Verilog provides the cmos primitive, which internally connects an nmos and pmos in parallel between the source and drain. The transmission gate passes both strong 0 and strong 1 without the threshold voltage drop that a single nmos switch would suffer when passing a logic 1. This makes it essential for analog-friendly digital signal passing.

Power supplies in switch-level modeling are declared using supply1 for VDD (strong logic 1) and supply0 for GND (strong logic 0). These are net types in Verilog, not parameters. The supply nets carry the highest signal strength, ensuring that transistors connected to them pull output fully to the rail.

Switch-level modeling also introduces the concept of signal strength, which is unique to this abstraction level. Signals in Verilog carry both a logic value and a strength. As a signal passes through resistive switches or switch chains, its strength degrades. When two signals of different strengths conflict on the same wire, the stronger one wins. Strengths from weakest to strongest are: highz, small, medium, weak, large, pull, strong, supply.

Mathematical Expression

The behavior of a CMOS gate at switch level follows directly from transistor network theory. For a CMOS inverter, when input A is logic 1, the NMOS forms a pull-down path from output to GND, and the PMOS is off. Output is 0. When input A is logic 0, the PMOS forms a pull-up path from VDD to output, and NMOS is off. Output is 1. This gives the truth: Out = NOT(A), but derived from transistor connectivity rather than a gate primitive.

For a CMOS NAND gate with two series NMOS transistors (controlled by A and B) and two parallel PMOS transistors, the output is 0 only when both A and B are 1, otherwise the parallel PMOS network pulls it to 1. This gives Out = NOT(A AND B). The switch-level model can directly verify this transistor topology.

Practical Understanding

Switch-level modeling is used when RTL or gate-level abstraction is insufficient. For example, when designing SRAM cells, pass transistor logic, or analyzing charge sharing in dynamic CMOS, transistor-level Verilog is necessary. It allows simulation of the exact circuit topology using a digital simulator rather than requiring SPICE.

Transmission gates are particularly important in multiplexer implementations and tri-state busses where bidirectional signal passing is required. In standard CMOS library cells, transmission gate-based multiplexers are area-efficient compared to static logic implementations, and switch-level Verilog describes these accurately.

Given:
A CMOS inverter modeled at switch level.
supply1 vdd; supply0 gnd;
wire in = 1'b0;
wire out;

Why this formula applies:
pmos conducts when gate=0, nmos conducts when gate=1.
With in=0: pmos(gate=0) is ON, nmos(gate=0) is OFF.

Formula:
pmos p1(out, vdd, in);
nmos n1(out, gnd, in);

Substitution:
in = 0 → pmos ON: out connected to vdd (supply1)
       → nmos OFF: no path to gnd

Calculation:
out driven by supply1 through pmos → out = 1 (supply strength)
No conflict from nmos side.

Final Answer:
out = 1'b1 at supply strength. Inverter output is correct.

Exam Tip: In GATE and university exams, remember that pmos conducts on gate=0 and nmos on gate=1. A common trap is confusing the port order of switch primitives. Verilog syntax is: nmos(output, input, gate) not (gate, input, output). The cmos transmission gate takes four ports: cmos(out, in, nctrl, pctrl) where nctrl and pctrl must be complementary for full conduction.

Switch-Level Concepts: Key Points

• nmos(out, in, gate): conducts when gate=1; pmos(out, in, gate): conducts when gate=0.
• rnmos and rpmos are resistive versions that weaken signal strength as it passes through.
• cmos(out, in, nctrl, pctrl): transmission gate passing bidirectional signals; requires nctrl and pctrl to be complementary.
• supply1 and supply0 declare VDD and GND nets at maximum signal strength.
• Signal strength degrades through resistive switches; stronger signal wins when two conflict on a wire.
• CMOS inverter at switch level uses one pmos from VDD and one nmos to GND, both gated by the same input.

Quick Revision

• nmos ON when gate=1; pmos ON when gate=0; mirrors real MOSFET behavior.
• Port order: nmos(output, input, gate) — output comes first in Verilog switch primitives.
• Transmission gate (cmos) passes both 0 and 1 without degradation; used in mux and bus designs.
• supply1/supply0 are net types for VDD/GND, not parameters or variables.
• Strength hierarchy: supply > strong > pull > weak > highz; conflict resolved by higher strength.
• rnmos/rpmos weaken signal strength; useful for modeling resistive pull-up/pull-down networks.
• GATE trap: confusing port order of switch primitives or nmos/pmos gate polarity.