Modeling Flip-Flops

Flip-flops are the fundamental storage elements of sequential digital systems, and modeling them correctly in Verilog is one of the most critical skills for RTL design. Sequential circuits in Verilog are described using always blocks with clock sensitivity, and the way the always block is structured determines whether the synthesized hardware is a D flip-flop, T flip-flop, JK flip-flop, or a latch. GATE aspirants and RTL designers must understand both the behavioral description and the hardware it maps to.

Core Concept Explanation

In Verilog, a flip-flop is inferred when an always block uses a clock edge in its sensitivity list and assigns to a reg variable using non-blocking assignment (<=). The sensitivity list @(posedge clk) tells the simulator to execute the block only on rising edges of the clock. This structural pattern is what synthesis tools recognize as a flip-flop, and it maps directly to a D flip-flop in the target technology library.

The D flip-flop is the most basic sequential element. Its Verilog model captures the input D on every rising edge of the clock and presents it at output Q after the clock edge. Any combinational logic that feeds the D input determines the next state of the flip-flop, which is how state machines and pipelined datapaths are built.

The T flip-flop toggles its output when T=1 and holds its value when T=0. In RTL, this is modeled as if(t) q <= ~q; else q <= q; inside a clocked always block. The T flip-flop is commonly used in counter design because feeding the carry signal as T to successive flip-flops directly implements a ripple counter.

The JK flip-flop is the most general flip-flop. When J=0,K=0 it holds; J=0,K=1 it resets to 0; J=1,K=0 it sets to 1; J=1,K=1 it toggles. The JK toggle condition makes it versatile. In Verilog, a case statement on the concatenated {j,k} input cleanly describes all four conditions. However, in modern synthesis, JK flip-flops are almost always implemented using D flip-flops with combinational logic at the D input.

Mathematical Expression

The characteristic equations of the three flip-flop types are the mathematical link between input and next state. For the D flip-flop: Q(n+1) = D. For the T flip-flop: Q(n+1) = T XOR Q(n). For the JK flip-flop: Q(n+1) = J.Q'(n) + K'.Q(n). These equations are the foundation for excitation table derivations used in state machine design and are directly testable in GATE.

Conversion between flip-flop types is another important topic. To implement a T flip-flop using a D flip-flop, the D input is driven by D = T XOR Q. To implement a JK flip-flop using a D flip-flop, the D input is driven by D = J.Q' + K'.Q. These conversions are derived directly from the characteristic equations by setting Q(n+1) from one type equal to the next-state formula of the other type.

Practical Understanding

In RTL design, the choice between asynchronous reset and synchronous reset has significant timing implications. An asynchronous reset is included in the always block sensitivity list (@(posedge clk or posedge rst)) and resets the flip-flop immediately when rst goes high, independent of the clock. This is useful for power-on initialization but requires careful timing to avoid reset release metastability.

A synchronous reset is NOT included in the sensitivity list. The always block still triggers only on the clock edge, and the reset condition is checked inside the block with if(rst) q <= 0; else q <= d;. The flip-flop resets only on the next clock edge after rst is asserted. Synchronous resets are preferred in high-speed designs because the reset signal goes through the data path and is subject to the same setup and hold constraints as any other signal, making timing analysis simpler.

Given:
T flip-flop with async reset, T = 1'b1 (always toggle mode).
Initial Q = 0. Clock period = 10ns. Reset deasserted at t=0.

Why this formula applies:
Q(n+1) = T XOR Q(n). With T=1, Q toggles every clock edge.
Async reset: any posedge rst clears Q immediately.

Formula:
always @(posedge clk or posedge rst)
  if (rst) q <= 1'b0;
  else if (t) q <= ~q;
  else q <= q;

Substitution:
t = 1 always.
t=0: Q=0. After clk posedge: Q = 1 XOR 0 = 1
t=10ns: Q=1. After clk posedge: Q = 1 XOR 1 = 0
t=20ns: Q=0. After clk posedge: Q = 1 XOR 0 = 1

Calculation:
Sequence: 0 -> 1 -> 0 -> 1 -> ... (divide-by-2 behavior)

Final Answer:
T FF with T=1 generates 5ns period output (half of 10ns clock). Used as frequency divider.

Exam Tip: The single most common GATE trap in flip-flop modeling is the placement of rst in the sensitivity list. Async reset: always @(posedge clk or posedge rst) with if(rst) checked first. Sync reset: always @(posedge clk) with if(rst) inside — rst NOT in sensitivity list. Synthesis tools infer async reset only when rst appears in the sensitivity list. Also remember: always use non-blocking assignments (<=) for sequential logic to avoid simulation race conditions.

Quick Revision

• D FF characteristic equation: Q(n+1) = D. RTL: always @(posedge clk) q <= d;
• T FF characteristic equation: Q(n+1) = T XOR Q. T=1 toggles, T=0 holds.
• JK FF characteristic equation: Q(n+1) = J.Q' + K'.Q. JK=11 toggles, JK=00 holds.
• Async reset: rst in sensitivity list; resets independent of clock edge.
• Sync reset: rst NOT in sensitivity list; reset takes effect only at next clock edge.
• Always use non-blocking assignment (<=) in clocked always blocks; blocking (=) causes simulation race conditions and incorrect synthesis.
• GATE trap: writing @(posedge clk) for async reset (wrong) or putting rst in sensitivity list for sync reset (wrong). The presence or absence of rst in the sensitivity list completely determines async vs sync behavior.