Module Instantiation

In Verilog, designing complex digital systems is accomplished by connecting smaller, reusable modules together. Module instantiation is the mechanism by which one module creates and connects instances of another module, forming a structural hierarchy. This concept is fundamental to structural modeling and mirrors how actual hardware is assembled from standard cells and IP blocks.

Core Concept Explanation

A module in Verilog is a self-contained hardware description with defined input and output ports. When another module wants to use it, it instantiates that module by giving it an instance name and connecting ports to local signals. Every instance is independent, meaning you can instantiate the same module multiple times and each copy operates as a separate hardware unit.

The syntax follows the pattern: module_name instance_name ( port_connections );. The module name refers to the already-defined Verilog module. The instance name is a unique identifier you assign to this particular copy. Port connections are how you wire the sub-module ports to signals in the parent module.

There are two ways to specify port connections. The first is positional port mapping (by order), where signals are listed in the exact same order as the ports were declared inside the module definition. This is compact but fragile. If the port order changes in the sub-module definition, the instantiation silently misbehaves without any error.

The second and recommended method is named port mapping (by name), where each port is explicitly connected using the dot notation: .port_name(signal_name). This style is independent of port declaration order and makes the code far more readable and maintainable in large designs.

Mathematical Expression

Module instantiation does not carry a single formula, but the concept of port width matching is critical. If a module port is declared as input [3:0] a, then the connected signal in the parent must also be at least 4 bits wide. A mismatch does not always cause a compilation error in Verilog but leads to unintended bit truncation or zero-padding, which is a common design bug.

The hierarchy depth in a structural design is bounded by synthesis tool limits, but logically, a module can contain instances of other modules to any depth, as long as no module instantiates itself (no direct recursion). The total gate count of a design is the sum of gate equivalents of all leaf-level module instances across the full hierarchy.

Practical Understanding

In real ASIC and FPGA flows, structural Verilog produced by synthesis tools uses module instantiation extensively. Each standard cell, whether a NAND gate, a flip-flop, or a multiplexer, is a module. The netlist is a flat or hierarchical collection of instantiations. Understanding module instantiation allows students to read and verify synthesis output netlists, which is an important skill in verification.

Parameter passing during instantiation is another key feature. A module can be made generic using the parameter keyword, and each instance can override parameter values. For example, a generic adder module parameterized with WIDTH can be instantiated as an 8-bit adder in one place and a 16-bit adder in another, without rewriting any logic.

Given:
A module 'adder' with ports: input [3:0] a, input [3:0] b, output [4:0] sum
Top module has wires: wire [3:0] x = 4'b1010, wire [3:0] y = 4'b0110, wire [4:0] result

Why this formula applies:
Module instantiation connects parent signals to sub-module ports.
Named mapping ensures correct connection regardless of port order.

Formula:
adder instance_name (.port(signal), .port(signal), ...);

Substitution:
adder u1 (.a(x), .b(y), .sum(result));

Calculation:
Internally: sum = a + b = 4'b1010 + 4'b0110 = 5'b10000

Final Answer:
result = 5'b10000 (decimal 16). Named mapping correctly wired all ports.

Exam Tip: In GATE questions, named port mapping is always safe when port order in the module definition is not shown. Positional mapping requires knowing the exact declaration order. Also note that unconnected output ports in an instantiation are legal in Verilog but unconnected input ports default to high-impedance (z), which can cause unexpected behavior.

How Module Instantiation Works: Key Points

• Syntax is module_name instance_name (port_list); where instance_name must be unique within the parent module.
• Named mapping uses .port_name(signal) syntax and is independent of port declaration order inside the sub-module.
• Positional mapping lists signals in the exact order ports were declared; any port reordering in the sub-module breaks the connection silently.
• Parameters can be overridden at instantiation using #(parameter_value) or defparam, enabling generic reusable designs.
• The same module can be instantiated multiple times with different instance names; each instance is an independent hardware copy.
• Port width mismatches do not always produce errors; Verilog truncates or zero-pads silently, so careful width matching is mandatory.

Quick Revision

• Module instantiation: module_name instance_name (.port(signal)); creates a hardware copy of the sub-module inside the parent.
• Named mapping (.port(signal)) is preferred; positional mapping requires exact port declaration order.
• Parameters override: adder #(.WIDTH(8)) u1 (.a(x),.b(y),.sum(s)); allows width-generic modules.
• Unconnected inputs default to z (high-impedance); this can silently corrupt logic.
• No recursive instantiation is allowed; a module cannot instantiate itself.
• In synthesis netlists, every gate is a module instance; reading netlists requires fluency in instantiation syntax.
• GATE trap: positional mapping with reordered ports compiles without error but produces wrong hardware.