Port Connection Rules
Input, Output, Inout, reg/wire connection rules.
Verilog Port Rules
Test your knowledge on this topic.
Question 1 of 3
Q1.Which data type must an internal signal have to be driven by a module's input port?
Related Articles
Introduction to HDLs
Verilog vs VHDL, simulation vs synthesis.
12 min read
Verilog Module Structure
Module, ports, endmodule, instance hierarchy.
4 min read
Vectors and Arrays
Declaring buses, memories, reg [7:0] mem [0:255].
4 min read
Data Types and Logic Values
Net (wire), Register (reg), 4-value logic (0,1,x,z).
9 min read
PLI Basics
Programming Language Interface C/C++ connection.
11 min read