Port Connection Rules

In Verilog, every module communicates with the outside world through ports. Understanding the rules governing how ports are declared, typed, and connected is fundamental to writing correct synthesizable designs. Errors in port connections are among the most common causes of simulation mismatches and synthesis failures in digital design.

Core Concept: Port Directions and Data Types

Every Verilog port has two attributes: a direction and a data type. The direction is either input, output, or inout. The data type is either wire or reg. These two attributes together determine what can drive the port and where the driven value can be used.

An input port is always a wire by default and can never be declared as reg. This is because an input port receives a value driven by an external source, so the module itself does not need to store it. Inside the module, an input port acts like a wire that continuously carries whatever the parent module drives onto it.

An output port defaults to wire but can be declared as reg when the port is driven from a procedural block such as an always block. If the output is driven by continuous assignment or by the output of a gate or submodule, it stays as wire. If it is assigned inside an always or initial block, it must be declared as reg.

An inout port must always be of type wire or a net type such as tri. It cannot be reg because inout ports represent bidirectional signals that can be driven from both sides. A procedural assignment cannot model bidirectional contention correctly, so reg is not allowed.

Port Connection Rules During Module Instantiation

When you instantiate a module, you connect its ports to signals in the parent module. The connecting signal in the parent must respect directionality. For an input port of the child module, the parent connects a wire or reg. For an output port of the child module, the parent must connect a wire, not a reg, because only nets can receive continuous driven values from outside a procedural context. For an inout port, both sides must be a net type.

Verilog supports two styles of port connection: positional connection and named connection. In positional connection, signals are listed in the same order as the port declaration. In named connection, each port is explicitly identified by name using the dot notation such as .portname(signal). Named connection is strongly preferred in industry because it avoids ordering errors and is self-documenting.

Unconnected ports also follow specific rules. If an input port is left unconnected in an instantiation, it receives a high-impedance value Z. If an output port is left unconnected, the driven value is simply ignored. This is legal but must be done intentionally, and tools often generate warnings for undriven or unconnected ports.

Practical Understanding: Reg vs Wire on Outputs

One of the most common beginner errors is forgetting to declare an output as reg when it is driven inside an always block. If you write always @(*) followed by an assignment to output y, and y is declared only as output y without the reg keyword, the simulator will throw a compile error because you are attempting a procedural assignment to a net type.

Conversely, if you declare an output as reg and then try to use a continuous assign statement to drive it, that is also an error. A reg cannot be driven by assign. It can only be assigned inside procedural blocks. Understanding this distinction prevents a large class of Verilog compilation errors.

In SystemVerilog, the logic type unifies wire and reg behavior, removing this confusion. But for standard Verilog, keeping the rule clear is essential: use output reg when the always block drives it, use plain output wire when assign or submodule output drives it.

Given:
A module with output y driven by an always block.
Input ports: a (1-bit), b (1-bit)
Output port: y (1-bit), driven inside always block

Why this formula applies:
Since y is driven in a procedural block, it must be declared as reg.
Input ports a and b are always wire by default.

Formula:
Port rule: output driven by always block => output reg
            output driven by assign       => output wire (default)
            input                         => always wire (default)

Substitution:
module and_gate (
  input  wire a,
  input  wire b,
  output reg  y
);
  always @(*) begin
    y = a & b;
  end
endmodule

Calculation:
If a=1, b=1 => always block triggers => y=1 (stored in reg y)
If a=0, b=1 => always block triggers => y=0

Final Answer:
y correctly holds the computed value as a reg-type output.
Declaring y as just 'output y' without reg would cause a compile error.

Exam Tip: In GATE and university exams, a common trap is a code snippet where an output is driven in an always block but declared without reg. Always check: if output is assigned in always, it must be reg. If driven by assign, it must be wire (or default).

Mechanism: How Port Types Are Resolved

• input ports are always wire by default and cannot be declared reg under any circumstance.
• output ports default to wire but must be declared reg if driven from an always or initial block.
• inout ports must always be a net type such as wire or tri; reg is not allowed.
• When instantiating a module, the parent connects a wire or reg to child input ports but must use a wire for child output ports.
• Named port connections using dot notation are preferred over positional connections to avoid ordering mistakes.
• An unconnected input port receives Z; an unconnected output port is legally ignored but generates a warning.

Quick Revision

• input is always wire. Never reg. Period.
• output reg is required when the output is assigned inside an always block.
• output without reg is a wire, driven by assign or submodule output.
• inout must be a net type (wire or tri). No procedural assignment allowed on inout.
• In instantiation: child output connects to parent wire, not reg.
• Named connection syntax: .portname(signal) prevents positional bugs.
• Exam trap: output y driven in always without reg keyword causes compile error.