Simulation Time

Simulation time control is a fundamental aspect of writing correct and meaningful Verilog testbenches. Without precise time management, signal sequences cannot be tested, setup and hold violations cannot be verified, and simulation cannot be stopped in a controlled way. Understanding the timescale directive and simulation control tasks is mandatory for both testbench engineers and GATE aspirants dealing with Verilog simulation questions.

Core Concept Explanation

The `timescale compiler directive defines two things: the time unit and the time precision for the module that follows it. The syntax is `timescale <time_unit>/<time_precision>. The time unit defines what value of 1 in a delay statement #1 corresponds to in real time. The time precision defines the smallest resolvable time interval, which controls how simulation rounds fractional time values.

For example, with `timescale 1ns/1ps, a delay of #10 advances simulation time by 10 ns. A delay of #10.5 would be valid because the precision of 1ps allows sub-nanosecond granularity. If the precision were 1ns instead, then 10.5 would be rounded to 11. Precision must always be less than or equal to the time unit. Using a finer precision increases simulation memory usage and runtime.

$time and $realtime

The $time system function returns the current simulation time as a 64-bit unsigned integer, scaled to the time unit of the current module. If the timescale is 1ns/1ps, then $time at 10.5 ns returns 10 because it truncates to the time unit. The $realtime function returns a real-valued floating point number and includes the fractional part. So at 10.5 ns, $realtime returns 10.5. For most testbench logging purposes, $time combined with %0t format specifier is sufficient.

$finish and $stop

The $finish task terminates the simulation and returns control to the operating system. It accepts an optional argument: $finish(0) prints nothing, $finish(1) (default) prints simulation time and location, and $finish(2) prints additional resource statistics. The $stop task pauses simulation and drops the simulator into an interactive command mode. From interactive mode, the user can inspect signals, set breakpoints, and resume simulation. $stop is useful for debugging, while $finish is used at the end of a testbench after all checks are complete.

Mathematical Expression

The relationship between delay values in code and actual simulation time is straightforward. If the timescale directive is `timescale T_unit / T_prec, then a delay of #N in the code represents a real time of N x T_unit. The precision T_prec determines the resolution of rounding for fractional delays. The total simulation time when $finish is called equals the sum of all delay increments executed in the initial and always blocks up to that point. For periodic clocks, the simulation time at the Nth edge is N x (half_period x T_unit).

Practical Understanding

A common real-world pattern is to define the clock in an initial block with a half-period delay and use a separate initial block to drive stimulus and eventually call $finish. The timescale directive should be placed at the top of every testbench file. If different modules in a design use different timescales, the simulator uses the timescale of the module where each delay statement appears.

In FPGA-targeted designs, timescale affects only simulation, not synthesis. The synthesizer ignores all delay annotations and timescale directives. However, for timing analysis after synthesis, the actual propagation delays reported by the tool must be consistent with the simulation timescale used in functional verification. Mismatches between functional simulation timescale and static timing analysis units are a common source of confusion in early design stages.

Given:
`timescale 1ns/1ps
Clock period = 20ns (half period = 10ns)
Simulation ends after 10 complete clock cycles

Why this formula applies:
Each #10 delay advances simulation by 10 x 1ns = 10ns
10 complete clock cycles = 20 rising edges + final delay

Formula:
  Simulation end time = Number_of_half_periods x T_unit

Substitution:
  Each half period: #10 -> 10 x 1ns = 10ns
  20 half periods for 10 full clock cycles: 20 x 10ns = 200ns
  $finish called after #200 from time zero

Calculation:
  $time at $finish = 200
  $realtime at $finish = 200.000 (no fractional part here)
  If clock were #10.5 (with 1ns/100ps timescale):
  $time = 210 (truncated integer, 21 x 10ns)
  $realtime = 210.0

Final Answer:
$time returns 200 (integer, in time units)
$realtime returns 200.0 (real, same here)
Simulation ends at 200ns with $finish(1) printing the time.

Exam Tip: $time returns a 64-bit integer truncated to the time unit. $realtime returns a real number with fractional time. Questions asking which returns 10.5ns when timescale is 1ns/1ps always have answer $realtime. $time would return 10.

Mechanism: Timescale Effect on Delay Resolution

• `timescale must be declared before the module keyword. It applies to the module immediately following it in the file.
• $time returns an integer scaled to the time unit. If timescale is 10ns/1ns, a real time of 50ns gives $time = 5.
• $realtime returns a floating point real number and reflects the actual simulation time including fractions down to the precision.
• $finish(1) is the default form and prints simulation time, location (file, line), and then terminates. $finish(0) terminates silently.
• $stop is most useful during testbench debugging. It allows waveform inspection and signal forcing through the simulator interactive console before resuming.

Quick Revision

• `timescale syntax: `timescale <unit>/<precision>. Unit defines #1 meaning. Precision defines smallest rounding granularity.
• Rule: precision must be <= time unit. Valid: 1ns/1ps. Invalid: 1ps/1ns.
• $time = 64-bit integer, truncated to time unit. $realtime = real number, includes fractional precision.
• $finish ends simulation and exits. $stop pauses simulation for interactive inspection and can be resumed.
• Formula: Real time of #N = N x time_unit. Example: `timescale 10ns/1ns, #5 -> 50ns real time.
• Exam trap: $time does NOT return fractional values even if precision allows it. Use $realtime for fractional time values.
• timescale affects simulation only. Synthesis tools ignore all delay annotations and timescale directives entirely.