Data Types and Logic Values

Verilog models hardware signals, and hardware signals do not just carry binary 0 or 1. They can be uninitialized, floating, or in conflict. To accurately represent all these real-world conditions, Verilog uses a four-value logic system and a carefully defined set of data types that map directly to hardware behavior.

Understanding data types is critical because using the wrong type causes simulation mismatches, synthesis warnings, and logic errors that are extremely difficult to debug. GATE questions frequently test whether a student knows when to use wire versus reg and what x and z mean in simulation context.

Core Concept: Net Types and Register Types

Verilog data types fall into two fundamental categories. Net types represent physical wires and connections in hardware. They do not store values on their own. They continuously reflect the value being driven onto them. The most commonly used net type is wire. If a wire has nothing driving it, its value is z (high impedance). If two drivers conflict, the wire takes on the value x (unknown).

Register types, most importantly reg, model storage elements in simulation. A reg holds its last assigned value until a new assignment is made. It is important to understand that despite the name, a reg does not always synthesize to a flip-flop. If assigned in a combinational always block (with a complete sensitivity list and no missing branches), it will synthesize to combinational logic. The reg keyword simply means the signal can be assigned inside a procedural block.

Other register types include integer (32-bit signed, used for loop counters), real (floating point, simulation only), and time (64-bit unsigned, used to capture simulation time). These types are not synthesizable and are used exclusively in testbenches and simulation models.

The Four Logic Values in Detail

The value 0 represents a driven logic low. The value 1 represents a driven logic high. These two correspond to standard digital logic levels. The value x represents an unknown state, which arises when a reg is never initialized or when two drivers force opposite values onto the same wire simultaneously. The value z represents high impedance, meaning the signal is floating and has no active driver. This is used in tristate bus designs where only one driver is active at any time.

The distinction between x and z is frequently tested. A wire that is not connected to any driver carries z. A reg that has not been assigned in simulation carries x. When an x propagates through combinational logic, the output also becomes x, which is how simulation tools flag potential design bugs.

Mathematical Expression: Default Values and Resolution

The logic resolution table for nets defines what value appears on a wire when multiple drivers are present. For a wired-AND (wand) net, if any driver forces 0, the result is 0 regardless of other drivers, following the AND truth table. For a wired-OR (wor) net, if any driver forces 1, the result is 1. For a standard wire, if two drivers conflict (one drives 0 and another drives 1), the result is x. This resolution is automatically computed by the simulator using the built-in strength model.

Solved Numerical Example

An 8-bit reg is declared and never assigned in simulation. A 4-bit wire is declared but left unconnected. Determine the value and bit-width of each signal at simulation time zero, and calculate the total number of unknown or floating bits across both signals.

Given:
reg  [7:0] data_reg;   // 8-bit register, never assigned
wire [3:0] data_wire;  // 4-bit wire, no driver connected

Why this formula applies:
reg default = x for every bit
wire default = z for every bit
Total indeterminate bits = sum of all x bits + sum of all z bits

Formula:
Total indeterminate bits = width_of_reg + width_of_wire

Substitution:
Total = 8 (all x from reg) + 4 (all z from wire)

Calculation:
data_reg  at t=0 : 8'bxxxxxxxx
data_wire at t=0 : 4'bzzzz
Total indeterminate bits = 8 + 4 = 12

Final Answer:
12 indeterminate bits total (8 unknown x bits, 4 high-impedance z bits).

Exam Tip: wire and reg are the most tested data types. Remember: wire is driven continuously by assign or module outputs. reg is assigned inside always or initial blocks. An output port driven by an always block must be declared reg, not wire. This distinction causes marks loss in GATE.

Practical Implication

In FPGA simulation, x propagation is a powerful debugging tool. If x values appear at the output of a design during simulation, it indicates either uninitialized registers or bus contention. Synthesis tools typically ignore x and z (treating them as 0), so a design that simulates with x errors may still synthesize and seem to work on hardware but produce intermittent incorrect behavior at runtime. Catching these in simulation is far cheaper than hardware debugging.

• wire represents a physical connection. It is driven by assign statements or module output ports and reflects the driven value continuously.
• reg is assigned inside procedural blocks (always, initial). It holds its last assigned value and does not require a continuous driver.
• Default value of wire is z (high impedance). Default value of reg is x (unknown). This difference is significant during simulation initialization.
• x propagates through combinational logic. If an x enters an AND gate with a 0, the output is 0. If it enters with a 1, the output is x.
• z is used in tristate bus designs where only one driver must be active at a time. All inactive drivers must output z to avoid bus contention.

Quick Revision

• Verilog uses 4-value logic: 0 (low), 1 (high), x (unknown), z (high impedance). All four can appear in simulation.
• wire is a net type: driven continuously by assign or module output. Default value is z.
• reg is a register type: assigned inside always or initial blocks. Default value is x.
• Key trap: output reg is required when the output is assigned inside an always block. Using wire for such an output causes a compile error.
• integer is a 32-bit signed register type used for loop variables. real and time are simulation-only types.
• x propagation in simulation reveals uninitialized registers and bus conflicts. Synthesis ignores x and treats it as don't-care, causing hidden hardware bugs.
• Two wire drivers with opposite values produce x on the wire (bus contention). wor and wand nets resolve multi-driver conflicts using OR and AND rules respectively.