2s Complement

The 2s complement system is the universal standard for signed integer representation in all modern processors, from the ARM Cortex-M series to AMD Ryzen. Every C program variable declared as int uses 2s complement storage.

Core Concept

To form the 2s complement of a binary number, invert all bits and add 1. The result represents the negative of the original number. Unlike 1s complement, 2s complement has only one representation of zero (all bits zero), which simplifies comparison logic and conditional branch instructions.

The range of an n-bit 2s complement number is −2ⁿ⁻¹ to +2ⁿ⁻¹−1. For 8 bits that is −128 to +127. Notice the asymmetry: one more negative number than positive. The value −128 in 8-bit 2s complement has no positive counterpart, and attempting to negate it causes overflow.

2s complement arithmetic uses a standard adder with no end-around carry. The carry-out from the MSB is simply discarded when the operation is subtraction. This is why a single 74LS283 can add or subtract signed numbers with only external XOR gates to conditionally invert the B input and Cin tied to 1 for the subtract operation.

Boolean Expression

The 2s complement of N in n bits is: −N = 2ⁿ − N = N̄ + 1. The signed value of a number with MSB=1 is computed as −2ⁿ⁻¹ + (remaining bits as unsigned). For example, 1101 in 4-bit 2s complement = −8 + 4 + 1 = −3.

Given:
  Add (+47) and (-23) using 8-bit 2s complement

Formula / Rule:
  A - B = A + 2s complement of B

Step by step:
  +47 in binary = 00101111
  +23 in binary = 00010111
  1s complement of 23 = 11101000
  2s complement of 23 = 11101001

  Add:
    00101111
  + 11101001
  ----------
   100010000  (9 bits)

  Carry out = 1, discard it.
  Result = 00011000

  00011000 = 16 + 8 = 24

Final Answer:
  47 + (-23) = +24  (correct)

Exam Tip: The GATE-level signed overflow rule for 2s complement: overflow occurs when the carry into the MSB and the carry out of the MSB are different. Equivalently, adding two positives gives a negative result, or adding two negatives gives a positive result. Discard the carry-out does not mean ignore overflow; overflow detection is separate from the carry discard rule.

Key Properties

• Negate a number: invert all bits, add 1
• One unique zero (all bits 0); no end-around carry needed
• Range (n-bit): −2ⁿ⁻¹ to +2ⁿ⁻¹−1; more negative values than positive
• Signed value when MSB=1: subtract 2ⁿ from the unsigned interpretation
• 74LS283 subtraction: tie Cin=1 and use 1s complement (XOR with 1) of B inputs
• Overflow: carry-in to MSB XOR carry-out of MSB = 1
• Used universally: ARM, x86, RISC-V, MIPS, Intel 8085, and all modern CPUs

Quick Revision

• 2s complement = invert all bits + 1
• Unique zero: only one representation, unlike 1s complement
• Range (8-bit): -128 to +127
• To find value of negative number: MSB contributes −2ⁿ⁻¹
• Subtraction: add 2s complement of subtrahend, discard final carry
• Overflow: carry into MSB ≠ carry out of MSB
• −128 in 8-bit 2s complement cannot be negated (no +128 in 8 bits)
• Exam trap: negating the most negative number (−2ⁿ⁻¹) causes overflow, often missed in GATE subtraction questions