Buffer Gate

Every FPGA I/O cell and DRAM data bus driver contains buffer gates. Without them, a single logic gate driving 50 pF of PCB trace would violate fan-out and corrupt data.

Core Concept

A buffer gate passes its input to its output unchanged: Y = A. Its purpose is not logical transformation but electrical drive strength. A standard gate output can source or sink only 4 mA. The 74HC244 octal buffer sources 8 mA per output at 5 V, enabling it to drive long PCB traces or multiple downstream inputs.

The tri-state buffer (three-state buffer) adds a third output state: high impedance (Hi-Z). Controlled by an output-enable pin (OE, usually active-low), the Hi-Z state electrically disconnects the output from the bus. The 74HC125 quad tri-state buffer is the standard part for shared bus designs — data buses in microcontroller systems use four to eight of them.

Propagation delay for 74HC244 is 6 ns at 5 V. Fan-out is 15 LSTTL loads — three times a standard gate. Supply voltage is 2 V to 6 V. The 74HC125 adds 1 ns for OE decode, giving 7 ns total delay. In 3.3 V systems, 74LVC125A is used with 3.3 V supply and 5 V-tolerant inputs.

Boolean Expression

Non-inverting buffer: Y = A. Tri-state buffer: Y = A when OE'=0; Y = Hi-Z when OE'=1. The Hi-Z state is not a logic level — it is an open circuit. Multiple tri-state buffers can share a bus safely only if at most one OE is active at any time.

Given:
  8-bit data bus with 4 tri-state buffers (74HC125)
  Only one buffer active at a time
  Buffer B2 selected: OE2'=0, others OE'=1
  Input to B2: A = 0b10110101

Formula / Rule:
  Y = A when OE'=0
  Y = Hi-Z when OE'=1

Step by step:
  B1: OE1'=1 --> Y1 = Hi-Z (disconnected)
  B2: OE2'=0 --> Y2 = A = 0b10110101 (drives bus)
  B3: OE3'=1 --> Y3 = Hi-Z (disconnected)
  B4: OE4'=1 --> Y4 = Hi-Z (disconnected)

  Bus value = Y2 = 0b10110101 = 0xB5

Final Answer:
  Bus carries 0xB5
  Only B2 drives the bus; others present high impedance
  If two OE pins are active simultaneously: bus contention (damage risk)

Exam Tip: Bus contention occurs when two tri-state outputs drive the same line simultaneously with opposite logic levels. This is a short circuit and can damage the IC. GATE asks about maximum number of devices that can drive a bus — the answer is always ONE at a time. Also: a buffer does NOT invert (Y=A), while an inverter does (Y=A'). Confusing the two in circuit analysis is a common mistake.

Key Properties

• 74HC244: octal non-inverting buffer, 6 ns at 5 V, IOL/IOH = 8 mA
• 74HC125: quad tri-state buffer, 7 ns at 5 V, OE active-low, fan-out 15
• 74LVC125A: 3.3 V supply, 5 V-tolerant inputs, 5.5 ns, for mixed-voltage boards
• Hi-Z state is not a logic level — it is electrically open (high impedance)
• At most one tri-state driver active on a shared bus — two active causes contention
• Buffer does not change logic value (Y=A); used for drive strength and isolation
• Supply voltage: 2–6 V (74HC); 1.65–3.6 V (74LVC)

Quick Revision

• Buffer: Y=A — no inversion, only increased drive strength
• Tri-state: Y=A when enabled; Y=Hi-Z when disabled
• 74HC244: 6 ns, 8 mA, 5 V — octal non-inverting buffer
• 74HC125: 7 ns, OE' active-low — quad tri-state for bus systems
• Bus contention: two active tri-state drivers on same line — causes IC damage
• Hi-Z is not 0 or 1 — it is a disconnected (floating) state
• Fan-out of 74HC244: 15 LSTTL loads vs 10 for standard gates
• Exam trap: treating Y=A as an inversion — buffer output equals input with no logic change