NOT Gate

The NOT gate, also called an inverter, is the simplest yet most essential logic gate in digital electronics. It takes a single input and produces the logical complement as output. Without the NOT gate, it would be impossible to implement complete Boolean logic, since AND and OR alone cannot form a logically complete set.

Every digital processor, memory cell, and communication system depends on inversion at some level. Understanding the NOT gate is prerequisite to studying flip-flops, latches, NAND and NOR universality, and De Morgan's theorem applications.

Core Concept Explanation

The NOT gate performs the complement operation on its single input. If input A is 0, output Y is 1. If input A is 1, output Y is 0. The output is always the logical opposite of the input. This inversion is represented mathematically as Y = A prime (written with an overbar or an apostrophe). The bubble symbol at the output of the gate's triangular body is the standard IEEE/ANSI representation of inversion.

In CMOS technology, a NOT gate is implemented using a single complementary pair of transistors: one PMOS and one NMOS connected in series between supply and ground with the input driving both gates. When input is high, NMOS turns on and PMOS turns off, pulling output to ground (low). When input is low, PMOS turns on and NMOS turns off, pulling output to supply (high). This complementary action is the most power-efficient logic operation in CMOS.

The IC 7404 is the standard TTL implementation of the NOT gate. It contains six independent inverters on a 14-pin DIP package. This hex inverter configuration is practical because inverters are needed frequently and in multiples across digital circuits.

Mathematical Expression

The Boolean expression for the NOT gate is:

Y = A' (A complement, also written as A-bar or NOT A)

Key Boolean identities involving the NOT operation include: double complement rule (A double prime = A), complement law (A AND A prime = 0, A OR A prime = 1), and De Morgan's theorems which relate NOT to AND and OR transformations. De Morgan's first theorem states that NOT(A.B) = A' + B' and the second states NOT(A+B) = A'.B'. These identities are extensively used in logic minimization, NAND/NOR-only implementation, and GATE problem solving.

Practical Understanding

The NOT gate is indispensable in generating active-low signals, driving complementary data lines, and building latches and flip-flops. An SR latch, for instance, is constructed from two cross-coupled NOR or NAND gates, both of which rely on the inversion property internally. Without inversion, memory elements like latches and flip-flops cannot be constructed.

In practical circuit boards, the NOT gate also serves as a signal buffer when configured in pairs (two inverters in series restore the original signal while improving drive strength). Single inverters are used to convert active-high chip enable signals to active-low form required by many memory ICs.

Given:
A Boolean expression F = (A.B)' to be evaluated for A=1, B=1

Why this formula applies:
NOT gate inverts the AND gate result
De Morgan: (A.B)' = A' + B'

Formula:
F = (A.B)'

Substitution:
F = (1.1)' = (1)' = 0

Alternatively using De Morgan:
F = A' + B' = 0 + 0 = 0

Final Answer:
F = 0
Both direct evaluation and De Morgan give the same result, confirming De Morgan's theorem.

Exam Tip: De Morgan's theorem is tested heavily in GATE. Remember: to complement any expression, invert the entire expression, swap AND with OR, and complement each variable individually. Applying De Morgan correctly is the key to NAND-only and NOR-only circuit conversions.

Quick Revision

• Boolean expression: Y = A' (complement of input). Single input, single output gate.
• Truth table has 2 rows: input 0 gives output 1, input 1 gives output 0.
• Standard IC: 7404 (Hex Inverter, six NOT gates on one 14-pin chip).
• Double complement rule: (A')' = A. Applying NOT twice restores original value.
• De Morgan 1: (AB)' = A' + B'. De Morgan 2: (A+B)' = A'.B'.
• In CMOS, NOT gate uses one PMOS and one NMOS transistor in series. It is the simplest and most efficient CMOS gate.
• Exam trap: NOT gate alone is not sufficient for all Boolean functions. AND+NOT or OR+NOT are required for completeness.