Subthreshold Conduction

In classical MOSFET theory, the transistor is considered fully off when the gate-to-source voltage VGS falls below the threshold voltage Vt. In reality, a small but non-zero drain current continues to flow even below Vt. This phenomenon is called subthreshold conduction or weak inversion, and it is one of the most critical effects in low-power VLSI design and leakage current analysis.

Core Concept: Physics of Subthreshold Current

Below the threshold voltage, the surface potential in the MOSFET channel is less than 2*phi_F (the strong inversion condition). In this weak inversion regime, the carrier concentration in the channel is very low but not zero. These carriers move primarily by diffusion (not drift), driven by a concentration gradient from source to drain. This is analogous to the exponential current in a forward-biased bipolar junction transistor.

The subthreshold current is exponentially dependent on VGS. Even a small increase in VGS increases the inversion charge at the surface exponentially. This is fundamentally different from the above-threshold region where current increases quadratically (for long-channel devices). In sub-100nm transistors, subthreshold leakage is a dominant component of static power dissipation.

Mathematical Expression: Subthreshold Swing

The subthreshold drain current is: ID_sub = I0 * exp((VGS - Vt) / (n * VT)), where VT = kT/q is the thermal voltage (approximately 26 mV at 300K), I0 is a process-dependent pre-exponential current, and n is the subthreshold slope factor (n greater than 1, typically 1.2 to 1.5).

The subthreshold swing S defines how sharply the transistor turns off. It is the change in VGS required to reduce ID by one decade (factor of 10). S = (dVGS / d(log10 ID)) = n * VT * ln(10) = 2.3 * n * kT/q. At room temperature with n = 1, S_ideal = 2.3 * kT/q = 60 mV/decade. In real devices, n greater than 1 so S is typically 70 to 120 mV/decade.

The subthreshold slope factor n = 1 + Cd/Cox, where Cd is the depletion capacitance and Cox is the oxide capacitance. Reducing the oxide thickness (increasing Cox) pushes n toward 1 and improves subthreshold swing. This is the transistor physics motivation behind using high-k gate dielectrics in advanced nodes.

Practical Understanding

In low-power VLSI, leakage current determines the static power consumption of a chip with billions of transistors. If one transistor has 1 nA of subthreshold leakage, a chip with 10^9 transistors has 1 A of leakage current, which is unacceptable. Threshold voltage optimization is central to the low-power vs. high-speed trade-off.

Increasing Vt reduces leakage exponentially but also reduces drive current and switching speed. Techniques such as multi-threshold CMOS (MTCMOS) use high-Vt transistors in standby paths and low-Vt transistors in critical speed paths. Power gating cuts off supply to idle blocks using high-Vt sleep transistors to eliminate leakage.

Given:
VGS = 0.3 V, Vt = 0.5 V, n = 1.4, T = 300 K
I0 = 100 nA
VT = kT/q = 0.026 V

Why this formula applies:
VGS < Vt, so transistor is in weak inversion (subthreshold region).

Formula:
ID = I0 * exp((VGS - Vt) / (n * VT))

Substitution:
ID = 100e-9 * exp((0.3 - 0.5) / (1.4 * 0.026))
ID = 100e-9 * exp(-0.2 / 0.0364)
ID = 100e-9 * exp(-5.495)

Calculation:
exp(-5.495) = 0.00410
ID = 100e-9 * 0.00410

Final Answer:
ID = 0.41 nA (subthreshold leakage current)

Exam Tip: The ideal subthreshold swing at room temperature is 60 mV/decade (when n = 1). Real devices always have S greater than 60 mV/decade. If a GATE problem states S = 60 mV/decade, it implies n = 1 (ideal case, no interface traps, thin oxide). Remember this lower limit.

• Subthreshold current is driven by carrier diffusion, not drift. It is exponentially dependent on VGS.
• Subthreshold swing S = 2.3*n*kT/q. The fundamental lower limit is 60 mV/decade at room temperature.
• n = 1 + Cd/Cox is always greater than 1 due to finite depletion capacitance. Thinner gate oxide reduces n.
• Subthreshold leakage is exponentially sensitive to Vt. A 60 mV increase in Vt reduces leakage by 10x.
• Leakage is a dominant static power component in advanced CMOS nodes with billions of transistors.

Quick Revision

• Subthreshold current: ID = I0 * exp((VGS-Vt)/(n*VT)). Exponential, not quadratic.
• Subthreshold swing S = 2.3 * n * kT/q = 60*n mV/dec at 300K.
• Ideal S = 60 mV/decade (n=1). Real devices always have S larger than 60 mV/dec.
• n = 1 + Cd/Cox. Reducing Cd or increasing Cox reduces n toward 1.
• Increasing Vt by 60 mV reduces subthreshold leakage by one decade (10x).
• Trap: Subthreshold swing is in mV/decade, not mV/V. Confusing units is a common GATE mistake.
• Power gating and MTCMOS are circuit techniques to manage leakage in low-power design.