Logical Effort

Choosing transistor sizes for minimum delay in a multi-stage logic path is a non-trivial optimization problem. Logical effort is a systematic framework developed by Sutherland, Sproull, and Harris that quantifies the delay contribution of each gate type and load, enabling optimal sizing and stage count decisions through simple algebraic reasoning.

The technique separates gate delay into two components: a part due to the gate's internal topology (logical effort) and a part due to the capacitive load it drives (electrical effort). By minimizing the product of these efforts across all stages, designers can determine the optimal number of stages and transistor sizes without iterative simulation.

Core Concept Explanation

In the logical effort framework, the delay through a single logic gate is expressed as d = g * h + p, where all quantities are normalized to the delay of a reference inverter driving an identical inverter (tau = 3RC in a typical CMOS model). The quantity g is the logical effort of the gate, h is the electrical effort (also called branching effort), and p is the parasitic delay due to internal junction capacitances.

The logical effort g of a gate measures how much harder the gate is to drive compared to an inverter. For an inverter, g = 1. For a 2-input NAND, the NMOS series stack doubles the effective NMOS resistance, so g = 4/3. For a 2-input NOR, the PMOS series stack doubles effective PMOS resistance (PMOS is already 2x slower), so g = 5/3. These values are derived from the ratio of input capacitance needed to achieve the same drive strength as a reference inverter.

The electrical effort h = Cout/Cin is the ratio of the load capacitance driven by the gate to the gate's own input capacitance. Larger h means the gate drives a heavier load relative to its own size. To achieve the same delay budget, a gate driving a large load must itself be made larger, which increases Cin and reduces h for a fixed Cout.

Mathematical Expression

For a path through N stages, the total path delay is:

D = sum over i from 1 to N of (gi * hi) + P_total

where P_total is the sum of all stage parasitic delays. The path logical effort is G = product of all gi. The path electrical effort is H = C_out_path / C_in_path. The path branching effort B accounts for any signal fanout along the path. Total path effort F = G * B * H.

The minimum achievable delay for a path is obtained when the stage effort f = F^(1/N) is equal for all stages, where f is the per-stage effort gh. The optimal per-stage effort minimizing delay is typically around 4 for CMOS processes, which gives a rule of thumb: choose N stages such that F^(1/N) is close to 4. The minimum path delay is then:

D_min = N * F^(1/N) + P_total

Practical Understanding

Logical effort guides both the number of stages to use and the sizes of each stage. When the total path effort F is large, adding an extra buffer stage reduces the per-stage effort, which can reduce total delay even though more stages means more parasitic delay. The optimal N from the formula above balances these two effects.

In practice, synthesis tools use logical effort principles internally when sizing standard cells. A designer using this framework manually can quickly identify the bottleneck stage in a path, estimate whether re-ordering or restructuring logic will help, and choose between NAND-heavy versus NOR-heavy implementations based on g values.

The framework also applies to complex gates. A 3-input NAND has g = 5/3 due to three NMOS in series. A 4-input NAND has g = 2. As gates grow wider, their logical effort increases, making them slower per unit of load driven. This is why decomposing wide gates into multiple stages often yields better speed despite the added inverter delays.

Given:
3-stage path: NAND2 -> INV -> INV
Path input cap = 1 unit, Path output load = 64 units
Logical effort: g_NAND2 = 4/3, g_INV = 1, g_INV = 1
Parasitic: p_NAND2 = 2, p_INV = 1, p_INV = 1
No branching: B = 1

Why this formula applies:
G = g1*g2*g3 = (4/3)*1*1 = 4/3
H = 64/1 = 64
F = G * B * H = (4/3) * 1 * 64 = 85.3
Optimal stage effort f = F^(1/N) = 85.3^(1/3)

Formula:
D_min = N * f + P_total

Substitution:
f = 85.3^(1/3) = 4.44
P_total = 2 + 1 + 1 = 4

Calculation:
D_min = 3 * 4.44 + 4 = 13.32 + 4 = 17.32 tau units

Final Answer:
Minimum path delay D_min = 17.32 tau
Optimal stage sizing: each stage should drive effort h_i = f / g_i
Stage 1 (NAND2): h1 = 4.44 / (4/3) = 3.33, Cout1 = 3.33 * Cin1

Exam Tip: Logical effort of a 2-input NAND is 4/3 and a 2-input NOR is 5/3. NOR is slower because PMOS transistors have lower mobility, so stacking them in NOR is more costly. Prefer NAND over NOR in critical paths.

• Single stage delay: d = g * h + p, where g is gate topology dependent and p is from junction cap.
• Path effort F = G * B * H is the product of logical, branching, and electrical effort.
• Minimum delay when all stages carry equal per-stage effort f = F^(1/N).
• Optimal N minimizes D_min = N * F^(1/N) + P; typically f around 4 gives best trade-off.
• NAND preferred over NOR in critical paths due to lower logical effort values.

Quick Revision

• Delay per stage: d = g*h + p. Inverter: g=1, p=1. NAND2: g=4/3, p=2. NOR2: g=5/3, p=2.
• Path effort F = G * B * H where G = product of gi, B = branching, H = total cap ratio.
• Optimal sizing: make all stage efforts equal at f = F^(1/N).
• D_min = N * F^(1/N) + P_total. Choose N to make F^(1/N) close to 4.
• Wider gates have higher g values: 4-input NAND g=2, making them slow for large fan-in.
• Exam trap: Minimum delay is not always achieved with fewest stages. Adding buffer stages helps when F is large.
• Tau = 3RC is the delay unit; normalized delay values are process-independent scaling factors.