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Contents

MOS Fundamentals

MOS Capacitor Structure Threshold Voltage NMOS/PMOS I-V Channel Length Modulation Subthreshold Conduction MOS Capacitances Velocity Saturation Hot Carrier Effect

CMOS Logic

CMOS Inverter CMOS NAND/NOR Complex Gates Pass Transistor Logic Transmission Gates Tri-State Buffers Elmore Delay Logical Effort

CMOS Circuits

CMOS Adders Carry Skip/Select CMOS Multipliers Booth Multiplier Transmission Gate Logic Barrel Shifter Domino Logic Circuits Level Shifters IO Pads

Sequential VLSI

Bistability Principle SR Latch D Latch D Flip-Flop JK Flip-Flop CMOS Setup and Hold Time Clock Skew and Jitter Synchronizers

Memory Design

SRAM 6T Cell SRAM Array Org DRAM 1T Cell DRAM Refresh Sense Amplifiers ROM/PROM Design Flash Memory Cell

Design Flow

VLSI Design Flow Design Entry Lambda Rules Layout Basics DRC LVS Parasitic Extraction

Low Power Design

Power Components Dynamic Power Reduction Leakage Power Reduction Power Gating DVFS

Other Topics

FinFET Technology SOI Technology Design for Testability Fault Models FPGA Architecture Elements

Other Subjects

Analog Electronics Digital Electronics Signals & Systems Control Systems Electromagnetic Theory Digital Communication Analog Communication Network Analysis Microprocessors Verilog HDL Power Electronics Embedded Systems DSP Electronic Devices

Section Progress100%

8 of 8 articles

Logical Effort

Delay optimization technique.

Updated: 19 March 2026

9 min read

Logical Effort

Test your knowledge on path delay optimization and sizing.

Question 1 of 3

Q1.What is the logical effort of a standard 2-input CMOS NAND gate?

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Pass Transistor Logic

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Complex Gates

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