JK Flip-Flop CMOS

The JK flip-flop is an extension of the SR flip-flop that eliminates the forbidden state by introducing a toggle function. In VLSI, the JK flip-flop is typically not available as a standalone standard cell but is understood as a functionally important circuit derived from the D flip-flop. Its CMOS implementation reveals important principles of feedback-based sequential logic.

Core Concept Explanation

The SR flip-flop has an invalid state when both S and R are high simultaneously, because it attempts to set and reset Q at the same time, driving both Q and Q-bar to the same logic level, which is undefined. The JK flip-flop resolves this by redefining the J=1, K=1 condition as a toggle operation: Q_next = Q-bar, meaning the output simply inverts on each active clock edge when both inputs are high.

In CMOS, the JK flip-flop is realized by modifying a D flip-flop with combinational logic at the input. The D input to the master latch is derived as: D = J.Q-bar + K-bar.Q. This expression synthesizes all four JK operating modes using the current output Q as feedback. The feedback path from Q and Q-bar back to the input logic is what distinguishes the JK from simpler flip-flops.

The four operating modes of the JK flip-flop are: J=0, K=0 gives Hold (Q unchanged); J=0, K=1 gives Reset (Q=0); J=1, K=0 gives Set (Q=1); J=1, K=1 gives Toggle (Q flips). These modes cover all useful sequential operations, making the JK flip-flop the most functionally complete single-bit storage element.

Mathematical Expression

The characteristic equation of the JK flip-flop is:

Q(n+1) = J . Q-bar(n) + K-bar . Q(n)

This equation captures all four modes in one expression. When J=K=0: Q(n+1) = 0 + Q(n) = Q(n), which is hold. When J=0, K=1: Q(n+1) = 0 + 0 = 0, which is reset. When J=1, K=0: Q(n+1) = Q-bar + Q = 1, which is set. When J=K=1: Q(n+1) = Q-bar + 0 = Q-bar, which is toggle.

In CMOS implementation, D = J.Q-bar + K-bar.Q is realized with 2 NAND gates and one inverter, added to a standard D flip-flop. This gives approximately 28 to 32 transistors in total for the full JK flip-flop.

Practical Understanding

The toggle mode of the JK flip-flop makes it directly useful for building frequency dividers and binary counters. When both J and K are tied to logic 1, the output Q divides the input clock frequency by 2 with each stage. Cascading n such stages produces a divide-by-2^n counter, which is a fundamental building block in digital clock synthesis circuits.

In ASIC and FPGA design, JK flip-flops are not always available as dedicated cells. Instead, synthesis tools infer them by combining a D flip-flop with input logic derived from the JK characteristic equation. The designer specifies behavior and the tool maps it to available cells.

A subtlety in the CMOS JK flip-flop is the race-around condition, which occurs in a simple SR-to-JK conversion when the clock pulse is long. If J=K=1 and the clock stays high for long enough, the output may toggle multiple times unpredictably. The master-slave or edge-triggered implementation eliminates this by sampling only at the clock edge.

Given:
JK flip-flop, initially Q=0
Input sequence: J=1,K=0 → J=1,K=1 → J=0,K=1 → J=1,K=1
Apply one clock edge per step

Why this formula applies:
Q(n+1) = J.Q-bar(n) + K-bar.Q(n)

Formula:
Q(n+1) = J.Q-bar + K-bar.Q

Substitution and Calculation:
Step 1 (J=1,K=0, Q=0): Q+ = 1.1 + 1.0 = 1     → Q=1 (Set)
Step 2 (J=1,K=1, Q=1): Q+ = 1.0 + 0.1 = 0     → Q=0 (Toggle)
Step 3 (J=0,K=1, Q=0): Q+ = 0.1 + 0.0 = 0     → Q=0 (Reset, already 0)
Step 4 (J=1,K=1, Q=0): Q+ = 1.1 + 0.0 = 1     → Q=1 (Toggle)

Final Answer: Output sequence: Q = 0 → 1 → 0 → 0 → 1

Exam Tip: The JK characteristic equation Q(n+1) = J.Q-bar + K-bar.Q must be memorized. GATE frequently gives a state sequence and asks which flip-flop type or which input conditions produced it. Use this equation to back-calculate J and K values from known Q(n) and Q(n+1) pairs.

JK Flip-Flop Internal Structure in CMOS

• Input NAND logic computes D = J.Q-bar + K-bar.Q, synthesizing all four JK modes from the current Q value.
• Master latch (active on CLK-bar) captures D when clock is low; slave latch (active on CLK) transfers to Q at rising edge.
• Feedback from Q and Q-bar to input gates is what makes toggle mode possible without a forbidden state.
• Total transistor count is approximately 28 to 32, higher than a plain D flip-flop due to input logic.

Quick Revision

• JK characteristic equation: Q(n+1) = J.Q-bar + K-bar.Q. Memorize this for GATE.
• Four modes: Hold (00), Reset (01), Set (10), Toggle (11).
• CMOS implementation: D flip-flop + input NAND logic + Q feedback. Approximately 28 to 32 transistors.
• Toggle mode with J=K=1 divides clock frequency by 2, used in ripple counters.
• Race-around condition is eliminated by edge-triggering (master-slave structure).
• Trap: In GATE state table problems, apply the characteristic equation step by step for each clock edge.
• Unlike SR flip-flop, J=K=1 is valid in JK and produces a defined toggle, not an invalid state.