DRAM Refresh

Because DRAM stores data as charge on a capacitor, and this charge leaks over time due to transistor and junction leakage currents, the stored data must be periodically restored before it degrades below a readable threshold. This process is called DRAM refresh. Refresh is not a simple operation. It consumes memory bandwidth, power, and requires careful management by the memory controller. In GATE and VLSI courses, questions on refresh timing, types of refresh, and power impact are common.

Core Concept: Why Refresh is Necessary

The storage capacitor Cs in a DRAM cell holds charge representing stored data. Leakage currents flowing through the off-state access transistor, reverse-biased PN junctions, and gate-induced drain leakage (GIDL) continuously discharge this capacitor. At room temperature, a typical DRAM cell can retain charge for 64 ms to several seconds. The memory controller must read and rewrite every cell within the retention time (tRET) to prevent data loss. This is done by asserting each wordline periodically, allowing the sense amplifier to read and immediately restore the charge.

A refresh cycle is electrically identical to a read cycle. The row is activated (wordline asserted), all cells in that row share charge with their bitlines, the sense amplifier fires and restores all cells in the row to full logic swing, and then the row is closed. The key difference from a regular read is that no column is selected. No data is actually transferred out of the DRAM. The refresh is purely an internal operation that refreshes every cell in a row simultaneously at the cost of one RAS (Row Address Strobe) cycle.

Mathematical Expression: Refresh Overhead

Modern DRAM is organized with 8192 rows per bank (a common JEDEC standard). The refresh window is 64 ms at 85 degrees C. To refresh all rows within this window, the memory controller must issue one refresh command every:

tREFI = tRFC_window / N_rows = 64 ms / 8192 = 7.8 microseconds (approximately)

Here tREFI is the average refresh interval per row and tRFC is the time taken to complete one refresh cycle (typically 110 to 350 ns for modern DDR4/DDR5 depending on capacity). The refresh overhead as a percentage of total bandwidth is: Overhead = tRFC / tREFI. For tRFC = 260 ns and tREFI = 7800 ns, overhead is approximately 3.3 percent. This bandwidth is permanently lost to refresh and cannot be used for normal read or write operations.

Practical Understanding: Types of Refresh

In auto refresh (AR), the memory controller periodically issues a refresh command. The DRAM internally uses a refresh row counter to cycle through all rows automatically. The controller does not need to provide row addresses. During each refresh cycle, the DRAM is unavailable for normal access for the duration of tRFC. This is the standard mode in DDR2/DDR3/DDR4 SDRAM used in desktops and servers.

In self refresh (SR), the DRAM enters a low-power mode (initiated by the controller setting CKE low) and handles all refresh operations internally using an on-chip timer and oscillator. No external clock or commands are required. Self refresh is used during standby modes in mobile devices and when the processor is in deep sleep. The refresh rate may be reduced compared to normal operation because operating temperature is typically lower, extending retention time.

In distributed refresh, the 8192 refresh cycles are spread evenly across the 64 ms window, one row every tREFI. This avoids the burst penalty of refreshing many rows at once (burst refresh), which would cause a much longer memory stall. Distributed refresh is preferred in real-time systems and embedded DRAM where predictable latency is critical.

Given:
Total rows to refresh: N = 8192
Refresh window: tRET = 64 ms (at 85 degrees C)
Time per refresh cycle: tRFC = 260 ns
Memory cycle time (read/write): tRC = 50 ns

Why this formula applies:
tREFI is the average time between consecutive refresh commands.
Overhead measures bandwidth lost to refresh.

Formula:
tREFI = tRET / N = 64 ms / 8192
Overhead = tRFC / tREFI

Substitution:
tREFI = 64e-3 / 8192 = 7.8125 us
Overhead = 260e-9 / 7812.5e-9

Calculation:
tREFI = 7.8125 microseconds
Overhead = 260 / 7812.5 = 0.03328 = 3.33 percent

Memory cycles lost per refresh:
Cycles_lost = tRFC / tRC = 260 ns / 50 ns = 5.2 cycles per refresh
Refresh commands per second = 1 / tREFI = 1 / 7.8125 us = 128,000 per second

Final Answer: tREFI = 7.81 microseconds. Refresh overhead = 3.33 percent of total memory bandwidth lost.

Exam Tip: In GATE, if asked for refresh interval with N rows and tRET window, directly use tREFI = tRET / N. Also remember: lowering temperature INCREASES retention time and REDUCES required refresh frequency, saving power. Doubling the number of rows doubles the refresh overhead for the same window.

Refresh Overhead and Temperature Dependence

• Refresh activates each row periodically so the sense amplifier can restore charge to the storage capacitor before it decays below the sensing threshold.
• Every refresh cycle is one RAS operation. All cells in the selected row are refreshed simultaneously. No data is read out during refresh.
• Auto refresh: Controller issues periodic ARF command. DRAM row counter advances automatically. Standard in DDR SDRAM.
• Self refresh: DRAM internally manages all refresh in low-power mode. No external clock needed. Used in mobile standby.
• Distributed refresh: One row per tREFI = 64ms/8192 = 7.81 us. Avoids burst stalls. Preferred in real-time embedded systems.
• Higher temperature accelerates leakage, reducing retention time and forcing faster refresh, increasing power consumption.

Quick Revision

• DRAM needs refresh because capacitor charge leaks. Retention time at 85C is 64 ms. All rows must be refreshed within this window.
• tREFI = tRET / N_rows = 64 ms / 8192 = 7.81 microseconds per row.
• Refresh overhead = tRFC / tREFI. Typically 3 to 5 percent of total bandwidth is permanently consumed by refresh.
• Auto refresh: controller driven, most common. Self refresh: internal timer, low power standby mode.
• Distributed refresh spreads refresh evenly. Burst refresh groups many rows, causing longer stalls.
• GATE trap: Refresh overhead increases with more rows per bank and with higher temperature. Doubling rows doubles refresh commands per second.
• Refresh is a read followed by restore. It is not a separate erase-rewrite operation. One RAS cycle refreshes one entire row.