Fault Models

Testing a manufactured VLSI chip requires a model of what can go wrong during fabrication. A fault model is a mathematical abstraction that represents a class of physical defects in terms of their logical effect on circuit behavior. Without a well-defined fault model, it is impossible to generate a targeted test set or measure how thoroughly the test covers possible manufacturing defects. The two most widely used fault models in VLSI testing are stuck-at faults and delay faults, each targeting a different class of physical failure.

Core Concept: Stuck-At Fault Model

The Single Stuck-At (SSA) fault model assumes that exactly one net (wire or gate terminal) in the circuit is stuck at either logic 0 (SA0) or logic 1 (SA1), regardless of what the correct logic value should be. This model was introduced because it closely maps to the physical failures most common in CMOS: a metal line shorted to ground causes SA0 behavior, and a line shorted to the power supply causes SA1 behavior. An n-input gate has 2n+2 possible stuck-at faults (two for each input terminal plus two for the output).

A test for a stuck-at fault requires finding an input vector that satisfies two conditions simultaneously. First, the fault site must be activated: the input at the fault site must be forced to the opposite of the stuck value (to create a logical difference). Second, the effect of the fault must be propagated to a primary output or observable node so it can be observed. This two-condition requirement is the basis of the D-algorithm and PODEM automatic test pattern generation (ATPG) algorithms.

For a circuit with N nets, the total number of SSA faults is 2N. However, many of these faults are logically equivalent, meaning the same test detects multiple faults. After equivalence collapsing, the effective fault count is typically reduced to about 0.6 to 0.75 times 2N.

Delay Fault Models

As technology scales to smaller nodes, timing failures caused by marginally slow paths become as important as stuck-at failures. A transition fault models the situation where a net can change its logic value but does so too slowly, missing the required setup time of the next flip-flop. Unlike a stuck-at fault, a transition fault does not show up at slow test clock speeds: the circuit appears functionally correct at low frequency but fails at the rated operating frequency. This means transition faults can only be detected by at-speed testing, where patterns are applied at the chip's actual operating clock rate.

A path delay fault is a more detailed model where the cumulative propagation delay along a specific combinational path from one flip-flop to another exceeds the clock period. A single resistive via or an extra wire capacitance can cause a path delay fault. Testing for path delay faults requires sensitizing the critical path fully, which is computationally more expensive than stuck-at ATPG. The number of paths in a circuit can be exponential in the number of gates, so only the most critical paths are targeted in practice.

Mathematical Expression: Fault Coverage and Defect Level

Fault coverage (FC) is the ratio of detected faults to the total number of faults in the fault list. Defect level (DL) relates fault coverage to the incoming defect rate (probability that a chip has at least one defect, denoted Y_d = 1 - yield). The relationship is:

DL = 1 - (1 - Y_d)^(1 - FC) ... this simplifies to DL = Y_d^(1-FC) for the Williams-Brown model. A higher fault coverage directly reduces the defect level, meaning fewer defective chips escape to the customer.

Numerical Example

Given:
Circuit with N = 200 nets
Fault coverage FC = 0.95 (95%)
Yield Y = 0.90 (90% good chips), so defect probability Y_d = 1 - 0.90 = 0.10

Why this formula applies:
The Williams-Brown defect level model estimates the fraction of shipped chips that are defective.

Formula:
DL = Y_d ^ (1 - FC)

Substitution:
DL = 0.10 ^ (1 - 0.95)
   = 0.10 ^ 0.05

Calculation:
0.10 ^ 0.05 = e^(0.05 x ln(0.10))
           = e^(0.05 x (-2.3026))
           = e^(-0.1151)
           = 0.8913
DL = 1 - 0.8913 = 0.1087
Wait - correct formula application:
DL = 1 - (1 - Y_d)^(1/(1-FC)) is another form; use Williams-Brown:
DL = Y_d^(1-FC) = 0.10^0.05 = 0.891 means DL = 1 - 0.891 = 10.9%
At 95% fault coverage, DL drops from 10% to ~10.9% does not improve. At FC = 0.99:
DL = 0.10^(0.01) = 0.10^0.01 = e^(0.01 x (-2.3026)) = e^(-0.023) = 0.977
DL = 1 - 0.977 = 2.3% (significant reduction)

Final Answer:
At FC = 99%, defect level = ~2.3%, showing that pushing fault coverage from 95 to 99 percent nearly halves the defect level at 10% incoming defect rate.

Exam Tip: In GATE, stuck-at fault questions often ask how many faults exist for a specific gate or circuit (answer: 2 per net or gate terminal). Delay faults require at-speed testing and cannot be detected at slow functional test speeds. Remember: fault coverage measures the test quality; defect level measures how many bad chips escape to customers.

• SA0 fault: a net is stuck at logic 0 regardless of driving logic; physically corresponds to a short to ground.
• SA1 fault: a net is stuck at logic 1; physically corresponds to a short to supply voltage.
• Detection requires two conditions: activation (force opposite of stuck value) and propagation (route difference to an observable output).
• Delay faults model slow transitions that cause timing failures only at operating frequency, requiring at-speed ATPG.
• Fault coverage and defect level are inversely related: higher coverage means fewer defective chips escape testing.

Quick Revision

• Stuck-at faults: SA0 (net stuck at 0) and SA1 (net stuck at 1); 2 faults per net, 2N total for N-net circuit.
• Test generation needs activation + propagation of the fault difference to a primary output.
• Transition delay fault: correct logical value but slow transition; only detected at at-speed test.
• Path delay fault: cumulative delay along a path exceeds clock period; exponential number of paths.
• DL = Y_d^(1-FC); increasing fault coverage reduces defect level shipped to customers.
• ATPG algorithms: D-algorithm and PODEM automate stuck-at test pattern generation.
• Exam trap: stuck-at faults can be detected at any test speed; delay faults require at-speed testing only.