Threshold Voltage

The threshold voltage (Vt or Vth) is arguably the single most important parameter of a MOSFET in VLSI design. It defines the gate-to-source voltage at which the transistor transitions from the off-state to the on-state by forming an inversion layer at the silicon surface. Every key performance characteristic of a digital circuit, including switching speed, leakage current, noise margin, and power consumption, is directly influenced by the value of Vt.

Core Concept Explanation

When VGS is zero or below threshold, the p-type semiconductor surface under the gate is either in accumulation or in mild depletion. No conducting path exists between the n+ source and n+ drain regions. Current flow is negligible (only leakage). As VGS increases, holes are repelled from the surface, exposing negatively charged acceptor ions, and a depletion region forms. At VGS = Vt, a sufficient number of electrons are attracted to the surface to form a conducting inversion layer that connects source to drain. This is the strong inversion condition.

The threshold condition is precisely defined as the gate voltage at which the surface potential phi_s equals 2 x phi_F. This means the electron concentration at the surface equals the bulk hole concentration, indicating that the semiconductor surface has been inverted from p-type to effectively n-type behavior. For values of VGS above Vt, the transistor is on and drain current flows.

The threshold voltage is not a single fixed number for a given process. It depends on oxide thickness, substrate doping, gate material work function, oxide charges, and crucially on the voltage applied between the source and the body (substrate). This dependence on the source-body voltage is called the body effect or the back-gate effect.

Mathematical Expression

The basic threshold voltage expression for a p-type substrate NMOS device is:

Vt = Vfb + 2 phi_F + Qd_max / Cox

Where Vfb = phi_ms - Qox/Cox is the flat-band voltage, phi_ms is the metal-semiconductor work function difference, and Qox is the equivalent oxide charge density at the interface. The Fermi potential is phi_F = (kT/q) ln(Na/ni). The maximum depletion charge is Qd_max = q Na Xd_max where Xd_max = sqrt(4 epsilon_Si phi_F / (q Na)).

When a source-to-body voltage VSB is applied (source more positive than body), the depletion region widens and more charge must be induced in the semiconductor before inversion occurs. The modified threshold voltage is:

Vt(VSB) = Vt0 + gamma x (sqrt(2 phi_F + VSB) - sqrt(2 phi_F))

Where Vt0 is the zero-bias threshold voltage, and gamma is the body effect coefficient defined as gamma = sqrt(2 q epsilon_Si Na) / Cox. Note that gamma has units of sqrt(V). As VSB increases, Vt increases, meaning the transistor requires a larger gate voltage to turn on. This body effect is an important practical consideration in stacked transistor circuits and pass-gate logic.

Practical Understanding

In modern sub-100nm CMOS processes, Vt values are typically set in the range of 0.2V to 0.5V. Low Vt transistors switch faster but have higher subthreshold leakage current when off, increasing standby power. High Vt transistors have lower leakage but switch more slowly. Modern processes provide multi-Vt libraries where the same circuit can use a mix of low-Vt cells in timing-critical paths and high-Vt cells elsewhere to optimize both speed and power.

Oxide charges are an important practical modifier of Vt. Interface trapped charges and fixed oxide charges (typically positive for thermally grown SiO2) shift Vt in the negative direction for NMOS transistors. This shift must be compensated during process design, typically by adjusting the substrate doping through ion implantation of a channel implant specifically to set Vt to the desired value.

The body effect has direct implications in digital circuit design. In CMOS logic gates, the NMOS transistors in series stacks (like a three-input NAND gate) experience increasing source-to-body voltage as you move away from the output node. The transistor farthest from the output node has the highest VSB and therefore the highest Vt, making it the bottleneck for current flow and increasing the gate's propagation delay.

Given:
NMOS: Na = 5 x 10^16 cm^-3, tox = 8 nm
Vfb = -0.8 V, ni = 1.5 x 10^10 cm^-3
kT/q = 0.026 V, eps_Si = 1.04 x 10^-12 F/cm
eps_ox = 3.45 x 10^-13 F/cm
VSB = 1 V (body effect calculation)

Why this formula applies:
Vt = Vfb + 2*phi_F + Qd_max/Cox and body effect Vt(VSB) uses gamma.

Formula:
phi_F = (kT/q)*ln(Na/ni)
Xd_max = sqrt(4*eps_Si*phi_F / (q*Na))
Qd_max = q*Na*Xd_max
Cox = eps_ox/tox
gamma = sqrt(2*q*eps_Si*Na)/Cox
Vt0 = Vfb + 2*phi_F + Qd_max/Cox
Vt(VSB) = Vt0 + gamma*(sqrt(2*phi_F+VSB)-sqrt(2*phi_F))

Substitution:
phi_F = 0.026 * ln(5e16/1.5e10) = 0.026 * 15.11 = 0.393 V

Xd_max = sqrt(4 * 1.04e-12 * 0.393 / (1.6e-19 * 5e16))
        = sqrt(1.635e-12 / 8e-3) = sqrt(2.04e-10)
        = 14.3 nm

Qd_max = 1.6e-19 * 5e16 * 14.3e-7 = 1.144e-8 C/cm^2

Cox = 3.45e-13 / 8e-7 = 4.31e-7 F/cm^2

Vt0 = -0.8 + 2(0.393) + 1.144e-8/4.31e-7
    = -0.8 + 0.786 + 0.0265 = 0.0125 V approx 0.013 V

gamma = sqrt(2 * 1.6e-19 * 1.04e-12 * 5e16) / 4.31e-7
      = sqrt(1.664e-14) / 4.31e-7
      = 1.29e-7 / 4.31e-7 = 0.299 V^0.5 approx 0.3

Vt(VSB=1) = 0.013 + 0.3*(sqrt(0.786+1) - sqrt(0.786))
           = 0.013 + 0.3*(sqrt(1.786) - sqrt(0.786))
           = 0.013 + 0.3*(1.336 - 0.887)
           = 0.013 + 0.3*0.449
           = 0.013 + 0.135 = 0.148 V

Final Answer:
Vt0 = 0.013 V, Vt at VSB=1V = 0.148 V.
Body effect increases Vt by 0.135 V when VSB = 1 V.

Exam Tip: In GATE problems on body effect, always note that VSB is source-to-body voltage, which is positive when source is at higher potential than body (substrate). For NMOS with grounded substrate, VSB = VS. As more transistors stack in series, lower transistors have higher VS and thus higher Vt. This is a common trap in delay estimation questions.

Quick Revision

• Vt is the gate-to-source voltage required to form a conducting inversion layer connecting source to drain.
• Vt = Vfb + 2 phi_F + Qd_max / Cox. Each term has a specific physical meaning.
• phi_F = (kT/q) ln(Na/ni) is the Fermi potential. Higher doping means larger phi_F and larger Vt.
• Body effect: Vt(VSB) = Vt0 + gamma x (sqrt(2phi_F + VSB) - sqrt(2phi_F)). Vt increases with VSB.
• gamma = sqrt(2 q eps_Si Na) / Cox is the body effect coefficient in units of sqrt(V).
• Thinner oxide (smaller tox) increases Cox, decreases Qd_max/Cox term, and reduces gamma, lowering Vt and body effect strength.
• Exam trap: Body effect increases Vt for NMOS. Never confuse VSB (source-to-body) with VBS (body-to-source). For NMOS with grounded body, VSB equals source voltage potential.