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Contents

MOS Fundamentals

MOS Capacitor Structure Threshold Voltage NMOS/PMOS I-V Channel Length Modulation Subthreshold Conduction MOS Capacitances Velocity Saturation Hot Carrier Effect

CMOS Logic

CMOS Inverter CMOS NAND/NOR Complex Gates Pass Transistor Logic Transmission Gates Tri-State Buffers Elmore Delay Logical Effort

CMOS Circuits

CMOS Adders Carry Skip/Select CMOS Multipliers Booth Multiplier Transmission Gate Logic Barrel Shifter Domino Logic Circuits Level Shifters IO Pads

Sequential VLSI

Bistability Principle SR Latch D Latch D Flip-Flop JK Flip-Flop CMOS Setup and Hold Time Clock Skew and Jitter Synchronizers

Memory Design

SRAM 6T Cell SRAM Array Org DRAM 1T Cell DRAM Refresh Sense Amplifiers ROM/PROM Design Flash Memory Cell

Design Flow

VLSI Design Flow Design Entry Lambda Rules Layout Basics DRC LVS Parasitic Extraction

Low Power Design

Power Components Dynamic Power Reduction Leakage Power Reduction Power Gating DVFS

Other Topics

FinFET Technology SOI Technology Design for Testability Fault Models FPGA Architecture Elements

Other Subjects

Analog Electronics Digital Electronics Signals & Systems Control Systems Electromagnetic Theory Digital Communication Analog Communication Network Analysis Microprocessors Verilog HDL Power Electronics Embedded Systems DSP Electronic Devices

Section Progress44%

4 of 9 articles

Booth Multiplier

Algorithm for signed multiplication.

Updated: 19 March 2026

12 min read

Booth Multiplier

Test your knowledge on signed multiplication algorithms.

Question 1 of 3

Q1.By what factor does Radix-4 Booth encoding reduce the total number of partial products?

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CMOS Adders

Ripple carry, Carry lookahead, Manchester carry chain in CMOS.

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Domino Logic Circuits

Precharge/Evaluate phases, cascade issues.

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Level Shifters

Interfacing different voltage domains.

7 min read

IO Pads

Input/Output buffers, ESD protection.

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Barrel Shifter

Shifting logic using pass transistors.

4 min read

CMOS Multipliers

Transmission Gate Logic