Elmore Delay

Estimating delay in complex RC interconnect networks during logic synthesis and physical design is computationally expensive if done through full circuit simulation. The Elmore delay model provides a fast analytical approximation of the dominant time constant in an RC tree, allowing designers to estimate propagation delay without running SPICE.

Elmore delay is particularly relevant in VLSI because transistor stacks in CMOS pull-up and pull-down networks can be modeled as series-parallel RC chains. Understanding Elmore delay helps in sizing transistors, ordering series transistors in a stack, and making quick delay trade-off decisions during design.

Core Concept Explanation

The Elmore delay model applies to RC tree networks: trees where there is exactly one resistive path from the source to any node, and capacitances are connected from each node to ground. This structure is a good model for CMOS transistor stacks and interconnect wires.

The Elmore delay to a specific node k in the tree is the sum over all capacitors Ci in the network of the product of Ci and the resistance shared between the path from source to node k and the path from source to node i. Informally, each capacitor Ci is weighted by the portion of total resistance that lies on both the path to Ci and the path to the output node.

This is equivalent to saying: Ci at node i is multiplied by the total series resistance that Ci must charge through when a step is applied at the source. For a linear chain of series resistors R1, R2, ..., Rn with capacitors C1, C2, ..., Cn at each intermediate node, the Elmore delay at the last node is:

Td = R1*C1 + (R1+R2)*C2 + (R1+R2+R3)*C3 + ... + (R1+...+Rn)*Cn

Mathematical Expression

Formally for an RC tree, the Elmore delay at output node k is:

Td(k) = sum over all nodes i of [ Ci * Ri_k ]

where Ri_k is the total resistance on the shared path between the source-to-node-i path and the source-to-node-k path. For a simple linear chain, Ri_k equals the sum of all resistors from the source up to the point where the two paths diverge, which for a chain is simply the sum of resistors up to min(i, k).

In CMOS stacks, each transistor in a series pull-down or pull-up chain contributes an on-resistance Ron and a drain/source diffusion capacitance Cdiff. The optimal transistor ordering in a stack is to place transistors whose input switches earliest closest to the output, and transistors switching late closest to the supply or ground rail. This minimizes Elmore delay because late-switching transistors charge fewer capacitors through the remaining resistance.

Practical Understanding

Elmore delay is used in static timing analysis tools and synthesis engines to quickly evaluate delay without simulation. When a cell library is characterized, the interconnect from one gate output to the next gate input is modeled as an RC tree, and Elmore delay gives the 50 percent propagation delay approximation.

For a chain of n identical inverters each with output resistance R and input capacitance C, the Elmore delay through the chain is n * R * C. For a wire modeled as distributed RC, the Elmore delay from one end to the other is (R_total * C_total) / 2, where the factor of 1/2 arises from the distributed nature of the capacitance.

The model is an approximation, not an exact value. It matches the first moment of the impulse response of the RC network. For heavily branched trees or when the RC network has significant inductance, Elmore delay becomes less accurate. Despite this, it remains the most widely used delay estimation method in VLSI design due to its simplicity and analytical tractability.

Given:
Linear RC chain: R1 = R2 = R3 = 1 kOhm
C1 = C2 = C3 = 50 fF
Find Elmore delay at node n3 (the output)

Why this formula applies:
Linear chain: path to n3 passes through R1, R2, R3
Capacitor C1 at n1: shared resistance with path to n3 = R1 = 1 kOhm
Capacitor C2 at n2: shared resistance = R1 + R2 = 2 kOhm
Capacitor C3 at n3: shared resistance = R1 + R2 + R3 = 3 kOhm

Formula:
Td(n3) = C1 * R1 + C2 * (R1+R2) + C3 * (R1+R2+R3)

Substitution:
Td = 50e-15 * 1e3 + 50e-15 * 2e3 + 50e-15 * 3e3

Calculation:
Td = 50e-12 + 100e-12 + 150e-12 = 300e-12 s

Final Answer:
Elmore delay Td = 300 ps at node n3

Exam Tip: For a distributed RC wire of total resistance R and total capacitance C, Elmore delay = RC/2, not RC. This factor of 1/2 is a common GATE trap when comparing lumped versus distributed interconnect delay.

• Each capacitor in the RC tree is charged through all resistors on the path from source to that capacitor.
• Elmore delay at output = sum of (Ci * resistance shared between path to Ci and path to output).
• For a linear chain: Td = R1*C1 + (R1+R2)*C2 + ... which grows quadratically with chain length.
• Distributed RC wire: Td = RC/2, since capacitance integrates from both ends.
• Optimal transistor ordering: place the transistor with the earliest-arriving input closest to the output node.

Quick Revision

• Elmore delay is first-moment approximation of RC network step response, widely used in timing analysis.
• Formula: Td = sum_i (Ci * Ri_shared) where Ri_shared = resistance on shared path to output.
• Linear chain of N identical R, C stages: Td at end = RC * N*(N+1)/2.
• Distributed RC wire: Td = R_total * C_total / 2.
• Transistor ordering in stack: earliest-switching input closest to output minimizes delay.
• Elmore delay is an approximation; it matches 50% delay for dominant-pole systems.
• Exam trap: Distributed wire delay = RC/2, not RC. Lumped single RC gives delay = 0.69*RC (69% of RC).