Design for Testability

As integrated circuits grow in complexity to contain billions of transistors, verifying that a manufactured chip functions correctly becomes an enormous challenge. Design for Testability (DFT) is a set of design techniques applied during the RTL and layout phases to make the manufactured chip easier and more efficient to test. Without DFT, internal nodes of a chip are inaccessible from the primary I/O pins, making fault detection incomplete. DFT solves this by intentionally adding hardware structures that expose internal state for testing.

Core Concept: Controllability and Observability

The fundamental goal of any DFT technique is to improve two properties of internal circuit nodes: controllability and observability. Controllability is the ability to set an internal node to a known logic value (0 or 1) by applying signals at the primary inputs. Observability is the ability to determine the logic value of an internal node by examining the primary outputs. Without DFT, deep internal flip-flops and combinational nodes have poor controllability and observability because they require long input sequences to reach and long propagation paths to observe.

DFT techniques directly address this by providing alternative access paths, either by converting sequential elements into a shift register chain (scan), by embedding test generation and response analysis hardware inside the chip (BIST), or by wrapping the chip boundary with testable cells (boundary scan).

Scan Chain Design

A scan chain works by replacing standard D flip-flops with scan flip-flops that have an additional multiplexer at their data input. A control signal called scan_enable (SE) selects between normal functional data (SE=0) and scan shift data from the previous flip-flop in the chain (SE=1). When SE=1, all flip-flops in the design form a long shift register. The test flow has three phases: shift in (load test pattern serially), apply (one clock in functional mode to capture response), then shift out (read captured response serially and compare with expected).

The scan coverage metric indicates what fraction of internal faults the scan chain can detect. Modern designs target 95 to 99 percent fault coverage. Adding more scan chains in parallel reduces the number of shift clocks needed, which shortens test time at the cost of additional pins. If a chip has N flip-flops divided into M parallel scan chains, the shift length per chain is N/M.

BIST: Built-In Self Test

BIST moves the test pattern generation and response evaluation hardware onto the chip itself. A Linear Feedback Shift Register (LFSR) generates pseudorandom test vectors with maximal length sequences, and a Multiple Input Signature Register (MISR) compresses the circuit output responses into a compact signature. At the end of BIST, the signature is compared to a known good signature. This eliminates the need for an external tester to supply patterns, which is particularly useful for embedded memories (Logic BIST, Memory BIST).

Boundary Scan and JTAG

Boundary scan, standardized as IEEE 1149.1 (JTAG), addresses the problem of testing connections between chips on a printed circuit board. Each I/O pin of the chip is wrapped with a boundary scan cell that can capture the pin value or drive a test value. These cells are chained together and controlled through a four-wire Test Access Port (TAP) consisting of TDI, TDO, TCK, and TMS signals. A TAP controller state machine governs the shift, capture, and update operations. Boundary scan can test board-level interconnect faults like open circuits and short circuits between chips without any physical probing.

Mathematical Expression: Scan Test Time

The time required to apply all scan-based test patterns depends on the number of patterns P, the number of flip-flops N, the number of parallel scan chains M, and the clock period T_clk. Each pattern requires N/M shift cycles to load, one apply cycle, and N/M shift cycles to unload:

T_test = P x (2 x N/M + 1) x T_clk

Numerical Example

Given:
Number of flip-flops N = 10000
Number of parallel scan chains M = 10
Number of test patterns P = 5000
Clock period T_clk = 10 ns

Why this formula applies:
Each pattern needs N/M shifts in, 1 capture clock, and N/M shifts out.

Formula:
T_test = P x (2 x N/M + 1) x T_clk

Substitution:
T_test = 5000 x (2 x 10000/10 + 1) x 10e-9
       = 5000 x (2000 + 1) x 10e-9
       = 5000 x 2001 x 10e-9

Calculation:
= 10005000 x 10e-9
= 0.10005 seconds
= approximately 100 ms

Final Answer:
Test time = ~100 ms for 10 parallel scan chains.
If M = 1 (single chain), test time = ~1000 ms (10x longer), showing the benefit of multiple chains.

Exam Tip: GATE and university exams frequently ask what scan_enable does and the three phases of scan testing (shift-in, capture, shift-out). Remember: BIST uses LFSR for pattern generation and MISR for response compaction. Boundary scan uses JTAG (IEEE 1149.1) and is used for board-level, not chip-level internal fault detection.

• Scan flip-flops have a MUX at input: SE=0 selects functional data, SE=1 selects previous FF output for shifting.
• Three phases of scan test: shift-in the test pattern, one capture clock in functional mode, shift-out and compare.
• BIST uses LFSR for pseudo-random pattern generation and MISR to compact responses into a signature for comparison.
• Boundary scan (JTAG) wraps each I/O pin with a scan cell, allowing board-level interconnect testing without physical probes.
• More parallel scan chains reduces test time but requires more chip I/O pins.

Quick Revision

• DFT improves controllability and observability of internal circuit nodes for manufacturing test.
• Scan chain: scan FF with MUX, controlled by scan_enable; three phases are shift-in, capture, shift-out.
• T_test = P x (2N/M + 1) x T_clk; more chains M reduces test time proportionally.
• BIST: LFSR generates patterns, MISR compacts responses; no external tester needed.
• Boundary scan (IEEE 1149.1 / JTAG): TAP controller, TDI/TDO/TCK/TMS; tests PCB-level interconnects.
• Scan coverage target: 95 to 99 percent in production designs.
• Exam trap: BIST is for chip-level testing without an ATE; boundary scan is for board-level interconnect testing, not internal faults.