CMOS Inverter

The CMOS inverter is the most fundamental building block of digital VLSI design. Every combinational and sequential circuit in a CMOS technology is ultimately derived from this single gate. Understanding its Voltage Transfer Characteristic (VTC), noise margins, and switching threshold is not just theoretical knowledge — it is the foundation for all CMOS logic analysis and directly tested in GATE examinations.

Core Concept Explanation

A CMOS inverter consists of one pMOS transistor connected between VDD and the output, and one nMOS transistor connected between the output and GND. Both gates are tied together as the input node, and both drains are tied together as the output node. When the input is low (logic 0), the pMOS is ON and nMOS is OFF, pulling the output to VDD. When the input is high (logic 1), the nMOS is ON and pMOS is OFF, pulling the output to GND. This complementary switching action is the origin of the term CMOS.

The key strength of CMOS over earlier NMOS-only or ratioed logic is zero static power dissipation. At both logic levels, only one transistor is ON and it connects the output to a supply rail through a near-zero resistance path, while the other transistor is OFF and presents an extremely high impedance. No DC current flows from VDD to GND in the steady state. Power is only consumed during switching transitions when both transistors are briefly ON and the load capacitor charges or discharges.

The Voltage Transfer Characteristic (VTC) plots Vout versus Vin for a DC sweep from 0 to VDD. The VTC exhibits five distinct operating regions as Vin sweeps from 0 to VDD, corresponding to different combinations of pMOS and nMOS operating modes (cutoff, linear, saturation). The shape of the VTC — particularly how steep the transition region is — directly determines the quality of the inverter as a logic gate.

Voltage Transfer Characteristic and Noise Margins

The switching threshold VM is the input voltage at which Vout = Vin, i.e., the point where the inverter output equals its input. At this point, both transistors are in saturation and the inverter operates as an amplifier with very high gain. VM is found by setting IDS_n = IDS_p and solving. For a symmetric inverter (where kn = kp, meaning the nMOS and pMOS are sized so their drive strengths are equal), VM = VDD/2.

The noise margin quantifies how much noise the gate can tolerate on its input without producing an incorrect output. Two critical points on the VTC are VOH (maximum output high voltage), VOL (minimum output low voltage), VIH (minimum input that is still interpreted as logic high), and VIL (maximum input interpreted as logic low). For an ideal CMOS inverter, VOH = VDD and VOL = 0. VIH and VIL are found where the VTC slope equals -1.

The Noise Margin High (NMH) = VOH - VIH and Noise Margin Low (NML) = VIL - VOL. For a symmetric inverter, NMH = NML = VDD/2 - VIL. A steeper VTC transition gives larger noise margins. This is why high-gain operation in the transition region is desirable — it makes the digital abstraction more robust.

Mathematical Expression

The switching threshold for a general (asymmetric) CMOS inverter is derived by equating the drain currents of nMOS and pMOS at saturation:

VM = (VTn + (sqrt(kp/kn)) × (VDD + VTp)) / (1 + sqrt(kp/kn))

Here, VTn and VTp are the threshold voltages of nMOS and pMOS respectively (VTp is negative), and kn = µn Cox (W/L)n, kp = µp Cox (W/L)p are the process transconductance parameters multiplied by the respective aspect ratios. For VM = VDD/2, we need kn = kp, which requires (W/L)p/(W/L)n = µn/µp ≈ 2 to 3 (since hole mobility is 2–3 times lower than electron mobility). This is why the pMOS transistor in a balanced inverter must be 2–3 times wider than the nMOS.

Practical Understanding

The propagation delay of a CMOS inverter is determined by how quickly the load capacitor CL can be charged or discharged. The high-to-low propagation delay tpHL depends on the nMOS pull-down strength, and tpLH depends on the pMOS pull-up strength. The average propagation delay tp = (tpHL + tpLH)/2. For a given technology, CL includes the drain capacitances of both transistors plus the input capacitance of the next stage and any wiring capacitance.

Sizing the inverter involves a tradeoff: a wider transistor drives larger loads faster (lower delay) but also presents a larger input capacitance to the previous stage. The concept of logical effort formalizes this tradeoff and allows optimal sizing of chains of gates for minimum delay. The inverter is the reference gate with logical effort of 1 for both nMOS and pMOS.

Given:
VDD = 1.8 V, VTn = 0.4 V, VTp = -0.4 V
kn = 200 µA/V^2 (nMOS W/L already factored)
kp = 80 µA/V^2 (pMOS W/L already factored)
sqrt(kp/kn) = sqrt(80/200) = sqrt(0.4) = 0.632

Why this formula applies:
Switching threshold VM = Vin where IDS_n = IDS_p (both in saturation).
Formula: VM = (VTn + sqrt(kp/kn) × (VDD + VTp)) / (1 + sqrt(kp/kn))

Substitution:
VM = (0.4 + 0.632 × (1.8 + (-0.4))) / (1 + 0.632)
VM = (0.4 + 0.632 × 1.4) / 1.632
VM = (0.4 + 0.8848) / 1.632

Calculation:
VM = 1.2848 / 1.632 = 0.787 V

Final Answer:
VM ≈ 0.787 V
Since VM < VDD/2 = 0.9 V, the switching threshold is skewed low,
meaning nMOS is stronger. Increase (W/L)p to shift VM toward 0.9 V.

Exam Tip: For GATE, remember that VM = VDD/2 only when kn = kp, which requires (W/L)p/(W/L)n = µn/µp ≈ 2–3. If a problem gives equal W/L for both transistors, VM will be skewed below VDD/2 because nMOS has higher µCox. NMH and NML are NOT equal in this asymmetric case.

Quick Revision

• CMOS inverter: pMOS pull-up (ON when Vin=0) + nMOS pull-down (ON when Vin=1). Complementary operation gives zero static power.
• VTC switching threshold: VM = (VTn + sqrt(kp/kn)×(VDD+VTp)) / (1+sqrt(kp/kn)). VM = VDD/2 only when kn = kp.
• To achieve VM = VDD/2, pMOS must be 2–3× wider than nMOS due to lower hole mobility.
• NMH = VOH - VIH, NML = VIL - VOL. For ideal CMOS: VOH=VDD, VOL=0. VIH and VIL found where dVout/dVin = -1.
• Static power = 0. Dynamic power = CL × VDD^2 × f. Short-circuit power exists during switching transitions.
• GATE trap: Wider pMOS means higher input capacitance at that node — there is always a sizing tradeoff between drive strength and input capacitance.
• Steeper VTC slope in transition region = larger noise margins = better noise immunity.