MOS Capacitor Structure

The MOS capacitor is the foundational structure of all MOSFET devices and VLSI technology. Before a MOSFET can be understood, the behavior of a simple metal-oxide-semiconductor sandwich under an applied voltage must be thoroughly understood. The MOS capacitor itself is not used as a standalone device in modern circuits, but it is the theoretical model that describes what happens at the silicon surface when voltage is applied, which directly determines transistor behavior.

Core Concept Explanation

The MOS capacitor consists of three layers: a metal (or heavily doped polysilicon) gate on top, a thin insulating silicon dioxide layer in the middle, and a doped semiconductor substrate at the bottom. A voltage applied between the gate and the substrate modifies the distribution of charge carriers near the semiconductor surface. This surface region directly beneath the oxide is called the channel region in a MOSFET.

The behavior of the MOS capacitor depends critically on the polarity and magnitude of the applied gate voltage. Three distinct regimes of operation exist: accumulation, depletion, and inversion. Each regime corresponds to a different charge distribution at the semiconductor surface, and understanding these regimes explains the complete operation of a MOSFET from off-state to on-state.

For a p-type substrate (which is the standard case for an n-channel MOSFET), the majority carriers are holes. When a negative voltage is applied to the gate, holes accumulate at the surface, increasing the majority carrier concentration above its equilibrium value. When a small positive voltage is applied, holes are repelled and a depletion region of immobile negative acceptor ions forms near the surface. When the gate voltage exceeds the threshold voltage, minority carrier electrons are attracted to the surface in sufficient numbers to form a conducting inversion layer of electrons.

Three Operating Modes in Detail

Accumulation Mode

In accumulation, the gate voltage for a p-type substrate is negative (VG less than 0). The electric field points from the substrate toward the gate, attracting holes toward the silicon-oxide interface. The surface hole concentration increases above the bulk value. The structure behaves like a parallel plate capacitor with capacitance per unit area equal to Cox = epsilon_ox / tox, where epsilon_ox is the permittivity of silicon dioxide and tox is the oxide thickness. In accumulation, the total capacitance equals Cox because the semiconductor surface is so heavily populated with holes that it acts like a conductor.

Depletion Mode

As VG increases above zero for a p-substrate, holes near the surface are repelled and a space charge region of immobile ionized acceptors forms. This depletion layer has a width Xd and a capacitance Cdep = epsilon_Si / Xd. The total measured capacitance drops below Cox because Cox and Cdep are now in series. The total capacitance is C_total = Cox x Cdep / (Cox + Cdep). As VG increases, Xd increases, Cdep decreases, and C_total decreases further until the depletion width reaches its maximum value.

Inversion Mode

When VG reaches the threshold voltage Vt, the surface potential phi_s equals 2 x phi_F, where phi_F is the Fermi potential of the bulk semiconductor. At this point, the electron concentration at the surface equals the bulk hole concentration, and a conducting inversion layer of electrons is formed. For VG greater than Vt, the depletion width stops increasing (it is pinned at Xd_max), and additional gate charge is balanced by the inversion layer charge. At high frequencies, minority carriers cannot respond fast enough, and the capacitance remains at its minimum value Cox x Cdep_max / (Cox + Cdep_max). At low frequencies, inversion charge responds fully and capacitance returns to Cox.

Mathematical Expression

The threshold voltage of the MOS capacitor is one of the most important expressions in VLSI design. The threshold voltage Vt for a p-substrate device is given by:

Vt = flat-band voltage Vfb + 2 x phi_F + Qd_max / Cox

Where Vfb is the flat-band voltage accounting for work function difference and oxide charge, phi_F = (kT/q) x ln(Na/ni) is the bulk Fermi potential, and Qd_max = q x Na x Xd_max is the maximum depletion charge per unit area. The maximum depletion width is Xd_max = sqrt(2 x epsilon_Si x 2 phi_F / (q x Na)).

Given:
p-type silicon substrate, Na = 10^16 cm^-3
ni = 1.5 x 10^10 cm^-3 at 300K
kT/q = 0.026 V at 300K
eps_Si = 11.7 x 8.854 x 10^-12 F/m = 1.036 x 10^-12 F/cm
Vfb = -0.5 V (assume for this example)
tox = 10 nm = 10 x 10^-7 cm
eps_ox = 3.9 x 8.854 x 10^-14 F/cm = 3.45 x 10^-13 F/cm

Why this formula applies:
Vt = Vfb + 2*phi_F + Qd_max/Cox

Formula:
phi_F = (kT/q) x ln(Na/ni)
Xd_max = sqrt(2 * eps_Si * 2*phi_F / (q * Na))
Qd_max = q * Na * Xd_max
Cox = eps_ox / tox
Vt = Vfb + 2*phi_F + Qd_max/Cox

Substitution:
phi_F = 0.026 x ln(10^16 / 1.5x10^10)
      = 0.026 x ln(6.67 x 10^5)
      = 0.026 x 13.41 = 0.348 V

Xd_max = sqrt(2 x 1.036e-12 x 2x0.348 / (1.6e-19 x 10^16))
        = sqrt(2 x 1.036e-12 x 0.696 / 1.6e-3)
        = sqrt(9.0e-10) = 30 nm approx

Qd_max = 1.6e-19 x 10^16 x 30e-7 = 4.8e-9 C/cm^2

Cox = 3.45e-13 / 10e-7 = 3.45e-7 F/cm^2

Vt = -0.5 + 2(0.348) + (4.8e-9)/(3.45e-7)
   = -0.5 + 0.696 + 0.0139
   = 0.21 V

Final Answer:
Vt = approximately 0.21 V for this p-substrate MOS capacitor.

Exam Tip: GATE frequently asks about C-V characteristics of MOS capacitors. Remember: accumulation gives Cox, depletion gives C less than Cox, inversion at high frequency gives minimum capacitance (C_min = Cox Cdep / (Cox+Cdep)), and inversion at low frequency returns to Cox. A common trap is to forget the frequency dependence in inversion.

Quick Revision

• MOS capacitor: Metal / SiO2 / p-Silicon stack. Gate voltage controls surface charge distribution.
• Accumulation (VG less than 0): holes pile up at surface. Capacitance = Cox.
• Depletion (0 less than VG less than Vt): depletion layer forms. C = Cox x Cdep / (Cox + Cdep), less than Cox.
• Inversion (VG greater than Vt): electron inversion layer forms. Depletion width pins at Xd_max.
• Threshold voltage: Vt = Vfb + 2 phi_F + Qd_max / Cox.
• High frequency inversion: minority carriers cannot follow AC. Capacitance stays at C_min.
• Exam trap: At low frequency in inversion, capacitance returns to Cox, not stays at minimum.