MOS Capacitor

The MOS capacitor is the structural heart of every MOSFET. Before understanding how a MOSFET amplifies or switches, it is essential to understand how the metal-oxide-semiconductor stack responds to an applied voltage. The MOS capacitor goes through three distinct operating regimes, accumulation, depletion, and inversion, each of which corresponds to a fundamentally different distribution of charge at the semiconductor surface.

Core Concept Explanation

A MOS capacitor consists of a metal electrode (gate), a thin insulating silicon dioxide layer, and a semiconductor substrate (commonly P-type silicon). When a voltage is applied to the gate relative to the substrate, an electric field penetrates through the oxide into the semiconductor and redistributes charges at the semiconductor surface. The behavior of the MOS capacitor is entirely determined by the polarity and magnitude of this gate voltage.

In the accumulation regime, a negative gate voltage is applied to a P-type substrate. The resulting electric field attracts the majority carriers (holes) toward the oxide-semiconductor interface. Holes pile up at the surface, forming a thin high-conductivity layer. The semiconductor near the surface looks even more P-type than the bulk. The capacitance in this regime is simply the oxide capacitance Cox = ε_ox/t_ox, which is the maximum capacitance.

When a small positive gate voltage is applied, holes near the surface are repelled into the bulk. A depletion region of width W forms at the surface, containing only fixed negative acceptor ions (ionized acceptors). No mobile carriers exist in this depletion layer. The MOS system now behaves like two capacitors in series: Cox (oxide) and Cd = ε_s/W (depletion layer). Total capacitance falls below Cox.

As the positive gate voltage is increased further, the surface potential increases and the Fermi level near the surface bends toward the conduction band. When the surface concentration of electrons exceeds the bulk hole concentration, inversion is said to occur. A thin channel of electrons (minority carriers) forms at the surface. The gate voltage at which inversion begins is the threshold voltage VT. This inversion layer is the conducting channel in a MOSFET.

Mathematical Expression

The oxide capacitance per unit area is Cox = ε_ox / t_ox, where ε_ox = 3.9 × ε_0 for silicon dioxide and t_ox is the oxide thickness. The maximum depletion width is Wmax = sqrt(4 × ε_s × |φF| / (q × NA)), where φF = (kT/q) × ln(NA/ni) is the Fermi potential, NA is the acceptor doping, and ε_s is the silicon permittivity.

The threshold voltage is VT = VFB + 2φF + Qd/Cox, where VFB is the flat-band voltage accounting for work function differences and oxide charges, 2φF is the surface potential needed for strong inversion, and Qd = q × NA × Wmax is the depletion charge per unit area. The condition ψs = 2φF (surface potential equals twice the Fermi potential) defines the onset of strong inversion.

Practical Understanding

The capacitance-voltage (C-V) characteristic of a MOS capacitor is a direct experimental tool for extracting device parameters. In accumulation, C = Cox (maximum). In depletion, C decreases as W increases. At inversion, the behavior differs between low-frequency and high-frequency measurements. At low frequency, the inversion layer can respond to the AC signal and C returns to Cox. At high frequency, the inversion charge cannot respond quickly enough and C stays at the minimum value Cmin = Cox × Cd/(Cox + Cd).

This high-frequency C-V behavior is frequently tested in GATE. The flat-band capacitance CFB is another important value that appears at a specific voltage between accumulation and depletion. Shifts in the C-V curve along the voltage axis indicate the presence of oxide charges or interface traps, which degrade MOSFET performance.

Given:
P-type Si with NA = 1e16 cm^-3, ni = 1.5e10 cm^-3
t_ox = 10 nm, ε_ox = 3.9 × 8.85e-14 F/cm = 3.45e-13 F/cm
ε_s = 11.7 × 8.85e-14 = 1.036e-12 F/cm, q = 1.6e-19 C, kT/q = 0.026 V

Why this formula applies:
Need to find threshold voltage using MOS capacitor theory.

Formula:
φF = (kT/q) × ln(NA/ni)
Wmax = sqrt(4 × ε_s × φF / (q × NA))
Qd = q × NA × Wmax
Cox = ε_ox / t_ox
VT = VFB + 2φF + Qd/Cox  (assume VFB = 0 for simplicity)

Substitution:
φF = 0.026 × ln(1e16 / 1.5e10) = 0.026 × ln(6.67e5) = 0.026 × 13.41 = 0.349 V
Wmax = sqrt(4 × 1.036e-12 × 0.349 / (1.6e-19 × 1e16))
     = sqrt(4 × 3.62e-13 / 1.6e-3) = sqrt(9.04e-10) = 3.01e-5 cm = 30.1 nm
Qd = 1.6e-19 × 1e16 × 3.01e-5 = 4.82e-8 C/cm²
Cox = 3.45e-13 / (10e-7) = 3.45e-7 F/cm²

Calculation:
VT = 0 + 2(0.349) + 4.82e-8 / 3.45e-7
   = 0.698 + 0.140

Final Answer:
VT ≈ 0.84 V

Exam Tip: In GATE, the condition for strong inversion is ψs = 2φF, not φF. A common error is using φF instead of 2φF in the VT expression. Also remember: VT increases with NA (heavier doping needs more gate voltage to invert).

Mechanism: C-V Characteristics Across Regimes

• Accumulation (VG < 0 for P-type): holes pile up at surface, C = Cox (maximum, oxide only).
• Depletion (0 < VG < VT): holes repelled, depletion width W grows, C = Cox in series with Cd = εs/W. C decreases as VG increases.
• Inversion (VG > VT): electron inversion layer forms at surface. W stops growing (Wmax). Depletion charge is fixed.
• At high frequency, the inversion charge cannot follow the AC signal. C stays at minimum (Cmin = Cox×Cd/(Cox+Cd)).
• At low frequency, inversion electrons respond to AC. C returns to Cox. This LF/HF split is a key GATE topic.

Quick Revision

• Three regimes: Accumulation (VG < VFB), Depletion (VFB < VG < VT), Inversion (VG > VT).
• Cox = ε_ox / t_ox. Cmin = Cox × Cd / (Cox + Cd). These are the two extreme capacitance values.
• Threshold voltage: VT = VFB + 2φF + Qd/Cox where Qd = q×NA×Wmax.
• Strong inversion condition: surface potential ψs = 2φF (not just φF).
• HF C-V: C stays at Cmin in inversion. LF C-V: C returns to Cox in inversion.
• Exam trap: Using φF instead of 2φF in VT expression is the most common error. Always use 2φF.
• Increasing NA increases φF and Wmax, which increases Qd/Cox term, raising VT. Heavier doping needs more gate voltage to invert.