IC Fabrication Basics

Integrated circuit fabrication is the sequence of precisely controlled physical and chemical processes used to build transistors, resistors, and interconnects on a silicon wafer. Understanding these steps is important not only for microelectronics engineers but also for device physics students because each fabrication step directly determines the electrical properties of the finished device. For GATE aspirants, questions on oxidation, diffusion, and lithography appear regularly in the Electronic Devices section.

Core Fabrication Steps

Thermal Oxidation

Thermal oxidation grows a silicon dioxide (SiO2) layer on the wafer surface by exposing it to oxygen or steam at temperatures between 800 and 1200 degrees Celsius. This SiO2 layer serves as a gate dielectric in MOSFETs, as a diffusion mask to block dopants from entering certain regions, and as an isolation layer between metal and silicon. The Deal-Grove model describes oxide growth: for thin oxides the growth is linear (reaction limited) and for thick oxides it becomes parabolic (diffusion limited).

Photolithography

Photolithography defines circuit patterns on the wafer. A photoresist is spun onto the wafer surface, then exposed through a photomask using ultraviolet light. Positive resist becomes soluble where exposed; negative resist hardens where exposed. After development, the exposed or unexposed resist is removed, revealing the underlying layer for the next processing step such as etching or ion implantation. The resolution of lithography is governed by the wavelength of light used and the numerical aperture of the lens system, following the Rayleigh criterion.

Etching

Etching removes material selectively from areas not protected by the photoresist. Wet etching uses chemical solutions (HF for SiO2, KOH for silicon) and is isotropic, meaning it etches equally in all directions. Dry etching (Reactive Ion Etching, RIE) uses plasma and is anisotropic, providing vertical sidewalls needed for submicron features. Dry etching is the dominant method in modern VLSI fabrication.

Ion Implantation and Diffusion

Ion implantation injects dopant atoms (boron, phosphorus, arsenic) directly into the silicon by accelerating them as ions to energies of 10 keV to several MeV. The depth of implantation is controlled by the ion energy and is characterized by the projected range Rp and its straggle (standard deviation). After implantation, the wafer is annealed at 900 to 1000 degrees Celsius to repair crystal damage and electrically activate the dopants by moving them onto substitutional lattice sites.

CVD and Metallization

Chemical Vapor Deposition (CVD) deposits thin films such as polysilicon, silicon nitride, or silicon dioxide from gaseous precursors. These films serve as gate electrodes, dielectric layers, or isolation spacers. Metallization deposits aluminum or copper to form interconnects. Modern processes use copper interconnects with a damascene process where trenches are etched, filled with copper, and then planarized using Chemical Mechanical Planarization (CMP).

Mathematical Expression

The Deal-Grove model for thermal oxide thickness x is:

x^2 + A*x = B*(t + tau), where B is the parabolic rate constant, B/A is the linear rate constant, t is the oxidation time, and tau accounts for initial oxide. For thin oxides (linear regime): x = (B/A)*(t + tau). For thick oxides: x = sqrt(B*t).

Practical Understanding

The minimum feature size in IC fabrication is called the critical dimension (CD). As per the Rayleigh criterion, CD = k1 * lambda / NA, where lambda is the wavelength of exposure light and NA is the numerical aperture. Modern nodes (7 nm, 5 nm) use extreme ultraviolet (EUV) lithography at 13.5 nm wavelength to achieve such fine patterns. Each generation of shrinking follows Moore's Law, which historically predicted doubling of transistor count approximately every two years.

Yield is a key practical metric: not all dies on a wafer will function correctly due to defects. Higher defect density reduces yield. Larger die sizes also reduce yield for the same defect density. Understanding yield trade-offs is important for IC manufacturing economics.

Given:
Oxidation time t = 60 min = 3600 s, Parabolic rate constant B = 0.0117 um^2/min (dry O2 at 1000 C)
Linear rate constant B/A = 0.304 um/min

Why this formula applies:
For moderate oxide thickness, use quadratic Deal-Grove equation

Formula:
x^2 + (B/(B/A)) * x = B * t
A = B / (B/A) = 0.0117 / 0.304 = 0.0385 um

Substitution:
x^2 + 0.0385*x = 0.0117 * 60 = 0.702

Calculation:
x^2 + 0.0385x - 0.702 = 0
Using quadratic formula: x = (-0.0385 + sqrt(0.0385^2 + 4*0.702)) / 2
x = (-0.0385 + sqrt(0.001482 + 2.808)) / 2
x = (-0.0385 + 1.6761) / 2
x = 1.6376 / 2

Final Answer: Oxide thickness x = 0.819 um (approximately 0.82 micrometers)

Exam Tip: For GATE, remember that wet oxidation grows oxide faster than dry oxidation because H2O is a smaller molecule and diffuses through SiO2 more quickly. Dry oxidation gives better interface quality and is used for gate oxides. Deal-Grove parabolic constant B is proportional to diffusivity of the oxidant.

• Thermal oxidation uses Deal-Grove model: linear growth at short times, parabolic at long times. Wet O2 grows oxide faster than dry O2.
• Photolithography: spin coat resist, expose through mask with UV light, develop, etch. Positive resist: exposed area dissolves.
• Dry etching (RIE) gives anisotropic profiles needed for fine features. Wet etching is isotropic and unsuitable for deep sub-micron.
• Ion implantation gives precise dopant dose and depth controlled by ion energy. Annealing is required to activate dopants.
• CVD deposits dielectric and poly-silicon films. CMP planarizes the surface before the next lithography level.
• Each photomask layer requires a separate lithography cycle. A modern CMOS process has 20 to 40 mask layers.

Quick Revision

• Oxidation: wet is faster (higher B), dry gives better quality gate oxide. Deal-Grove: x^2 + Ax = Bt.
• Lithography resolution: CD = k1*lambda/NA. Shorter wavelength = finer patterns. EUV uses 13.5 nm.
• Positive resist: exposed area dissolves. Negative resist: unexposed area dissolves. Positive is more common.
• RIE gives vertical walls (anisotropic). Wet etch gives rounded profiles (isotropic). Selectivity = etch rate ratio of target to mask.
• Ion implantation profile is Gaussian: peak at Rp, spread = delta-Rp (straggle). Higher energy = deeper Rp.
• Exam trap: Oxide growth consumes silicon (54% of oxide thickness comes from Si). For 0.1 um SiO2, 0.046 um of Si is consumed.
• CVD: LPCVD (low pressure) gives better uniformity and step coverage than APCVD (atmospheric pressure).