JFET Basics

The junction field-effect transistor is among the earliest FET devices and serves as the conceptual foundation for all field-effect transistor theory. Its operating principle, controlling drain current through a reverse-biased depletion region, introduces the idea of channel pinch-off and saturation that reappears in MOSFETs. Understanding JFET basics is essential for both circuit design courses and GATE Electronics.

Core Concept Explanation

The junction field-effect transistor (JFET) consists of a semiconductor channel (N-type for N-channel, P-type for P-channel) with ohmic contacts at each end called the source and drain. Along the sides of the channel, heavily doped gate regions of opposite polarity form p-n junctions. Current flows from drain to source through the channel and is controlled by the width of the channel.

The gate junction is always kept reverse biased during normal operation. A reverse bias voltage VGS applied between gate and source widens the depletion region extending into the channel. Since the depletion region is devoid of mobile carriers, it effectively narrows the conducting cross-section of the channel. A larger reverse VGS produces a wider depletion region and therefore a narrower channel, allowing less current to flow.

The pinch-off voltage VP is the gate-to-source voltage at which the depletion regions from both sides of the channel meet, completely blocking current flow. For an N-channel JFET, VP is negative (say −4 V). When VGS equals VP, the channel is pinched off and ID drops to near zero.

Importantly, pinch-off does not mean zero current in the saturation region. When VDS increases to the point where the channel at the drain end reaches pinch-off (VDS = VGS − VP), the current saturates rather than going to zero. The saturation occurs because the pinched-off region near the drain acts as a velocity-saturating barrier, not a complete blockade.

Mathematical Expression

In the saturation (pinch-off) region, the drain current follows a square-law relationship with VGS. This is the Shockley equation for JFETs: ID = IDSS × (1 − VGS/VP)^2, where IDSS is the drain current when VGS = 0 (maximum drain current) and VP is the pinch-off voltage.

In the ohmic (triode) region, where VDS is small, the drain current is given by ID = IDSS × [2(VGS/VP − 1)(VDS/VP) − (VDS/VP)^2]. For very small VDS, this simplifies to a linear resistance. The condition for entering saturation is VDS ≥ VGS − VP (noting that VP is negative for N-channel).

Practical Understanding

JFETs are depletion-mode devices, meaning they are ON at VGS = 0 and require a reverse gate bias to reduce current. This contrasts with enhancement-mode MOSFETs, which are OFF at VGS = 0 and need a forward gate bias to turn on. JFET gate current is essentially zero (only reverse saturation current of the gate junction), making it a high input impedance device suitable for sensor interfaces and audio preamplifiers.

In GATE, you are often asked to find the drain current at a given VGS using the Shockley equation, or to identify the operating region given VGS and VDS. Always check whether VDS is greater than or less than (VGS − VP) to determine the region. Remember that for N-channel, VP is negative, so (VGS − VP) is actually VGS + |VP|.

Given:
JFET parameters: IDSS = 8 mA, VP = −4 V
Applied: VGS = −1 V, VDS = 6 V

Why this formula applies:
Check region first: VGS − VP = −1 − (−4) = 3 V
VDS = 6 V > 3 V → Saturation region → use Shockley equation

Formula:
ID = IDSS × (1 − VGS/VP)^2

Substitution:
ID = 8 × (1 − (−1)/(−4))^2
   = 8 × (1 − 0.25)^2
   = 8 × (0.75)^2

Calculation:
ID = 8 × 0.5625

Final Answer:
ID = 4.5 mA

Exam Tip: For N-channel JFET, VP is negative. In the Shockley equation ID = IDSS(1 − VGS/VP)^2, the ratio VGS/VP is positive when VGS is negative (both negative). Do not mistakenly treat VP as positive — check sign carefully in GATE numerical problems.

Mechanism: Channel Pinch-Off

• At VGS = 0, channel is fully open and ID = IDSS (maximum drain current).
• As VGS becomes more negative (for N-channel), depletion regions widen symmetrically from both gate contacts, reducing effective channel cross-section.
• Pinch-off voltage VP is the VGS at which the channel is completely closed. For N-channel, VP is typically −2 V to −6 V.
• In the saturation region (VDS ≥ VGS − VP), channel is pinched off only near the drain end. ID becomes nearly constant and follows Shockley's square-law equation.
• JFET is a depletion-mode device. No forward gate bias is needed or allowed (that would forward bias the junction and create gate current).

Quick Revision

• JFET works by reverse-biased gate junction widening depletion region to narrow the channel.
• Shockley equation (saturation): ID = IDSS × (1 − VGS/VP)^2.
• Saturation condition: VDS ≥ VGS − VP (equivalently VDS ≥ |VP| + VGS for N-channel with negative VP).
• At VGS = 0: ID = IDSS (max). At VGS = VP: ID = 0 (cutoff).
• Gate current is essentially zero (reverse biased junction). High input impedance device.
• Exam trap: VP is negative for N-channel. Substituting without sign gives wrong answer. Always substitute signed values.
• JFET is always depletion-mode. Enhancement-mode JFETs do not exist in standard classification.