JFET Construction

A JFET controls a large drain current using only a voltage on its gate, drawing virtually zero gate current in normal operation. This makes it the preferred input transistor in electrostatic voltmeters, pH meters, and the front-end of guitar amplifiers where loading the source is unacceptable.

Core Concept

A JFET (Junction Field-Effect Transistor) consists of a bar of semiconductor (N-type for N-channel, P-type for P-channel) with a gate region of opposite doping diffused into it. In an N-channel JFET like the 2N5457, the channel carries conventional current from drain to source. The gate forms a reverse-biased p-n junction on either side of this channel.

Applying a negative voltage to the gate of an N-channel JFET (V_GS < 0) reverse-biases the gate junction more heavily. This widens the depletion region extending into the channel, reducing the channel cross-section and restricting current flow. At a sufficiently negative V_GS, the depletion regions from both sides meet at the center and completely block the channel. This voltage is the pinch-off voltage V_P (also written V_GS(off)).

The JFET is a depletion-mode device. It is fully ON with V_GS = 0 and turns off as V_GS becomes more negative (for N-channel). Gate current is essentially zero (below 1 nA) because the gate junction is always reverse biased. This gives the JFET an input impedance exceeding 10^9 Ω, far higher than any BJT.

Key Equations

Drain current in saturation: I_D = I_DSS × (1 - V_GS/V_P)^2 where I_DSS is drain current with V_GS = 0 (maximum drain current), V_P is pinch-off voltage (negative for N-channel, e.g. -4V), and V_GS is gate-source voltage.

Transconductance: g_m = -2 × I_DSS / V_P × (1 - V_GS/V_P) with units of mA/V (millisiemens). Maximum g_m occurs at V_GS = 0: g_m0 = -2 × I_DSS / V_P

Pinch-off condition (onset of saturation): V_DS(sat) = V_GS - V_P for drain current to enter saturation, V_DS must exceed this value.

Given:
  N-channel JFET: 2N5457
  I_DSS = 5 mA
  V_P = -4 V (pinch-off voltage)
  V_GS = -1 V (operating point)

Why this formula:
  In saturation, I_D follows the square-law equation.

Formula:
  I_D = I_DSS × (1 - V_GS/V_P)^2

Substitution:
  I_D = 5 × (1 - (-1)/(-4))^2
      = 5 × (1 - 0.25)^2
      = 5 × (0.75)^2

Calculation:
  I_D = 5 × 0.5625
      = 2.81 mA

  g_m = -2 × I_DSS / V_P × (1 - V_GS/V_P)
      = -2 × 5 / (-4) × (1 - 0.25)
      = 2.5 × 0.75
      = 1.875 mA/V

Final Answer:
  I_D = 2.81 mA at V_GS = -1V
  Transconductance g_m = 1.875 mA/V

Exam Tip: GATE frequently tests the sign of V_P and V_GS for N-channel versus P-channel JFETs. For an N-channel JFET, V_P is negative (typically -1V to -6V) and V_GS must be negative to reduce I_D. For a P-channel JFET, V_P is positive and V_GS must be positive. Substituting with wrong signs in the formula (1 - V_GS/V_P)^2 gives an answer greater than I_DSS, which is physically impossible.

Key Properties

• Depletion-mode device: ON at V_GS = 0, turns off as |V_GS| increases toward |V_P|.
• Gate current is below 1 nA because the gate junction is always reverse biased. Input impedance exceeds 10^9 Ω.
• I_DSS for 2N5457 is 1 mA to 5 mA. V_P is -0.5V to -6V. Both parameters vary widely between devices of the same type.
• Three terminals: Drain (D), Gate (G), Source (S). Symbol has an arrow on the gate indicating the p-n junction direction.
• N-channel JFET requires negative V_GS for control. P-channel JFET requires positive V_GS.
• JFET has positive temperature coefficient of resistance in the ohmic region, making parallel JFETs self-balancing unlike BJTs.
• Common N-channel JFETs: 2N5457 (signal), BF245 (RF), J113 (switch).

Quick Revision

• JFET = Junction FET. Controls channel current with reverse-biased gate junction.
• N-channel: V_GS negative, V_P negative. P-channel: V_GS positive, V_P positive.
• I_D = I_DSS × (1 - V_GS/V_P)^2 in saturation.
• I_D = I_DSS at V_GS = 0 (maximum current, fully open channel).
• I_D = 0 at V_GS = V_P (channel pinched off).
• g_m = -2 I_DSS / V_P × (1 - V_GS/V_P). Maximum at V_GS = 0.
• Gate input impedance > 10^9 Ω. Gate current < 1 nA.
• Exam trap: Forgetting that V_P is negative for N-channel leads to (1 - V_GS/V_P) > 1, giving I_D > I_DSS, which is impossible. Check signs before substituting.