MOSFET IV Characteristics

The MOSFET IV characteristics describe how drain current ID varies with drain-source voltage VDS and gate-source voltage VGS. Understanding these curves is essential for designing analog circuits, amplifiers, and switches using MOSFETs.

Unlike BJTs which are current-controlled devices, MOSFETs are voltage-controlled. The gate voltage determines whether the channel exists and how much current flows. For GATE aspirants, knowing the exact boundary conditions between operating regions and the role of channel length modulation is critical.

Core Concept Explanation

The characteristic curves below illustrate how drain current varies with voltage across different operating regions.

The MOSFET operates in three distinct regions. In the cutoff region, VGS is below the threshold voltage Vt, no inversion layer forms, and drain current is essentially zero. The device acts as an open switch.

When VGS exceeds Vt, an n-type channel forms between source and drain in an NMOS device. If VDS is small (VDS less than VGS minus Vt), the channel is uniform and the device behaves like a voltage-controlled resistor. This is the triode region (also called the linear region). Here, ID depends strongly on both VGS and VDS.

As VDS increases and reaches VGS minus Vt, the channel pinches off at the drain end. Further increase in VDS does not significantly increase ID because the pinch-off point simply moves toward the source. The device enters the saturation region, where ID is roughly constant for a fixed VGS.

In practice, ID does increase slightly with VDS even in saturation due to channel length modulation. As VDS increases beyond pinch-off, the effective channel length decreases slightly, increasing ID. This effect is modeled by the parameter lambda (λ), which is the channel length modulation coefficient.

Mathematical Expression

The drain current equations for an NMOS transistor are derived from the gradual channel approximation. In the triode region, ID depends on both VGS and VDS. In saturation, ID depends only on (VGS minus Vt) squared, reflecting the square-law behavior of MOSFETs. The parameter kn is the process transconductance parameter equal to (μn Cox W/L), where μn is electron mobility, Cox is oxide capacitance per unit area, W is channel width, and L is channel length.

Triode region (VDS less than VGS minus Vt): ID = kn [(VGS - Vt)VDS - VDS²/2]. Saturation region (VDS greater than or equal to VGS minus Vt): ID = (kn/2)(VGS - Vt)². With channel length modulation: ID = (kn/2)(VGS - Vt)²(1 + λVDS). The output resistance due to channel length modulation is ro = 1/(λID), which appears in small-signal models.

Practical Understanding

In analog circuit design, MOSFETs are almost always biased in the saturation region to function as amplifiers. The square-law ID equation means that the transconductance gm = dID/dVGS = kn(VGS - Vt) = sqrt(2kn ID), which is proportional to the square root of drain current. This is an important difference from BJTs where gm = IC/VT (linear in current).

Channel length modulation becomes more significant in short-channel devices. A smaller λ (larger 1/λ) means higher ro and better current source behavior. In analog design, maximizing ro is important for achieving high voltage gain. GATE problems often ask about the effect of λ on output resistance or small-signal gain.

In digital circuits, MOSFETs are switched between cutoff and triode (deep triode acts as a closed switch with low on-resistance RDS(on)). The triode region is also important in current mirrors and source degeneration circuits.

Given:
NMOS transistor: kn = 2 mA/V², Vt = 1 V, λ = 0.02 V⁻¹
VGS = 3 V, VDS = 4 V

Why this formula applies:
VDS = 4 V > VGS - Vt = 3 - 1 = 2 V → Saturation region
Channel length modulation included since λ is given.

Formula:
ID = (kn/2)(VGS - Vt)²(1 + λVDS)

Substitution:
ID = (2/2)(3 - 1)²(1 + 0.02 × 4)
ID = 1 × 4 × (1 + 0.08)

Calculation:
ID = 4 × 1.08 = 4.32 mA

Output resistance:
ro = 1/(λ × ID) = 1/(0.02 × 4.32 × 10⁻³) ≈ 11.57 kΩ

Final Answer:
ID = 4.32 mA, ro ≈ 11.57 kΩ

Exam Tip: In saturation, ID = (kn/2)(VGS-Vt)². Always verify region first: if VDS >= VGS-Vt, it is saturation. Many GATE problems give VDS=VGS (drain tied to gate) which always ensures saturation since VDS=VGS > VGS-Vt for Vt>0.

Mechanism: Region Boundaries and Channel Behavior

• Cutoff: VGS < Vt. No channel, ID ≈ 0. Device is OFF.
• Triode: VGS > Vt and VDS < (VGS - Vt). Channel exists uniformly. ID increases with VDS. Low VDS means linear resistor behavior.
• Saturation: VGS > Vt and VDS >= (VGS - Vt). Channel pinched off at drain. ID ≈ (kn/2)(VGS-Vt)². Amplifier operation region.
• Channel length modulation (λ): causes slight slope in ID vs VDS in saturation. Models finite output resistance ro = 1/(λID).
• gm = kn(VGS - Vt) in saturation. Transconductance increases with overdrive voltage (VGS - Vt).

Quick Revision

• Cutoff: VGS < Vt, ID = 0.
• Triode: VDS < (VGS - Vt). ID = kn[(VGS-Vt)VDS - VDS²/2].
• Saturation: VDS >= (VGS-Vt). ID = (kn/2)(VGS-Vt)²(1+λVDS).
• Channel length modulation coefficient λ causes ID to increase slightly with VDS in saturation.
• Output resistance ro = 1/(λID). Larger ro means better current source / higher gain.
• gm = kn(VGS-Vt) = sqrt(2kn·ID). gm is proportional to sqrt(ID) unlike BJT.
• Trap: Verify region before applying formula. If VDS = VGS (diode-connected), device is always in saturation.