PN Junction Formation

Every silicon diode and every bipolar transistor starts as a single crystal of silicon with a p-n junction at its heart. Understanding how this junction forms explains why a 1N4007 blocks 1000V in one direction and barely resists current in the other.

Core Concept

Pure silicon is a poor conductor. Adding a group-III element like boron creates p-type silicon with mobile holes as majority carriers. Adding a group-V element like phosphorus creates n-type silicon with free electrons as majority carriers. When these two regions are brought into contact, diffusion begins immediately.

Electrons from the n-side diffuse across the junction and fill holes on the p-side. This leaves behind positively charged donor ions on the n-side and negatively charged acceptor ions on the p-side. The exposed ions create an electric field pointing from n to p. This field opposes further diffusion and a balance is reached. The region swept free of mobile carriers is the depletion region, typically 0.1 to 1 µm wide in silicon.

The potential difference across the depletion region is the built-in voltage V0, approximately 0.6 to 0.7V for silicon at room temperature. No external source creates this voltage. It is a consequence of the carrier concentration gradient and cannot be used to drive current in an external circuit.

Key Equations

Built-in voltage: V0 = (VT) × ln(NA × ND / ni²) where NA = acceptor doping (cm⁻³), ND = donor doping (cm⁻³), ni = intrinsic carrier concentration ≈ 1.5 × 10¹⁰ cm⁻³ for Si at 300K, VT = 26 mV.

Depletion width: W = sqrt(2ε × V0 / q × (1/NA + 1/ND)) where ε = 11.7 × 8.85 × 10⁻¹² F/m for silicon, q = 1.6 × 10⁻¹⁹ C.

Width on p-side: xp = W × ND / (NA + ND)

Width on n-side: xn = W × NA / (NA + ND) The more heavily doped side has a narrower depletion width.

Given:
  NA = 10¹⁶ cm⁻³ (p-side, boron doped)
  ND = 10¹⁵ cm⁻³ (n-side, phosphorus doped)
  ni = 1.5 × 10¹⁰ cm⁻³ (Si at 300K)
  VT = 26 mV = 0.026 V

Why this formula:
  V0 comes from balancing the diffusion current against the drift current
  at thermal equilibrium.

Formula:
  V0 = VT × ln(NA × ND / ni²)

Substitution:
  V0 = 0.026 × ln(10¹⁶ × 10¹⁵ / (1.5 × 10¹⁰)²)

Calculation:
  ni² = (1.5 × 10¹⁰)² = 2.25 × 10²⁰
  NA × ND = 10³¹
  Ratio = 10³¹ / 2.25 × 10²⁰ = 4.44 × 10¹⁰
  ln(4.44 × 10¹⁰) = ln(4.44) + 10 × ln(10)
                   = 1.49 + 23.03 = 24.52
  V0 = 0.026 × 24.52 = 0.638 V

Final Answer:
  Built-in voltage V0 = 0.638 V ≈ 0.64 V

Exam Tip: GATE asks for V0 using the formula V0 = VT × ln(NA×ND/ni²). Always use ni = 1.5 × 10¹⁰ cm⁻³ for silicon and VT = 26 mV at 300K. A common mistake is to forget to square ni in the denominator. Also note that V0 is not the forward voltage drop across a diode in a circuit; it exists in equilibrium and cannot drive an external current. The 0.7V you use in circuit analysis is the applied forward voltage needed to reduce the depletion barrier to nearly zero.

Key Properties

• V0 ≈ 0.6–0.7V for silicon at 300K; about 0.3V for germanium (Ge).
• Depletion width W is inversely related to doping. Higher doping means narrower depletion on that side.
• The depletion region stores charge like a capacitor. This junction capacitance Cj is exploited in varactor diodes for tunable circuits.
• Built-in voltage increases with doping concentration and decreases with temperature (about -2 mV/°C for Si).
• Majority carriers (electrons in n, holes in p) are swept out of the depletion region; only fixed ions remain.
• The electric field in the depletion region points from n-side to p-side. This opposes hole diffusion from p to n and electron diffusion from n to p.

Quick Revision

• P-type: boron doped, majority carriers are holes.
• N-type: phosphorus doped, majority carriers are electrons.
• Depletion region: swept free of mobile carriers; contains fixed ions only.
• Built-in voltage V0 = VT × ln(NA×ND / ni²); approximately 0.7V for Si.
• V0 cannot drive external current; it is an internal equilibrium potential.
• Heavier doping → smaller depletion width on that side.
• ni = 1.5 × 10¹⁰ cm⁻³ for silicon at 300K; VT = 26 mV.
• Exam trap: confusing V0 (built-in voltage, ≈0.64V) with the diode forward voltage drop in a circuit (≈0.7V applied externally). They are related but not the same quantity.