JFET Self Bias

JFET self-bias sets the gate-source voltage automatically without a separate negative supply, which is why it appears in almost every single-supply JFET preamplifier circuit. Understanding where the Q-point lands on the transfer curve is the first skill a designer needs.

Core Concept

In JFET self-bias (also called source-bias), a resistor R_S is placed between the source terminal and ground. Since drain current flows through R_S, it creates a voltage V_S = I_D × R_S at the source. The gate is connected to ground through a large resistor R_G (typically 1 MΩ), so V_G = 0. Therefore V_GS = V_G - V_S = -I_D × R_S, which is automatically negative for an N-channel JFET.

The Q-point is found graphically by drawing the self-bias line V_GS = -I_D × R_S on the transfer characteristic. This is a straight line from the origin with slope -R_S. Where this line intersects the parabolic transfer curve I_D = I_DSS (1 - V_GS/V_P)^2, that is the operating Q-point. Both the Q-point I_D and V_GS are found simultaneously.

A bypass capacitor C_S is connected in parallel with R_S (typically 10 µF to 100 µF). At AC signal frequencies, C_S short-circuits R_S. This prevents AC degeneration of the signal, which would reduce voltage gain. Without C_S, the gain A_v = -g_m × R_D / (1 + g_m × R_S) instead of -g_m × R_D.

Key Equations

Self-bias line: V_GS = -I_D × R_S this is the load line on the transfer characteristic. Only two points needed to draw it: (0, 0) and (V_P, -V_P/R_S).

Q-point condition (substitute self-bias line into transfer equation): I_D = I_DSS × (1 + I_D × R_S / V_P)^2 solve this quadratic for I_D to find the exact Q-point current.

Small-signal voltage gain with bypass: A_v = -g_m × R_D. Without bypass capacitor: A_v = -g_m × R_D / (1 + g_m × R_S)

Given:
  N-channel JFET 2N5457
  I_DSS = 5 mA
  V_P = -4 V
  R_S = 1 kΩ = 1000 Ω
  R_D = 2 kΩ
  V_DD = 15 V

Why this formula:
  Q-point found by solving self-bias line and transfer curve simultaneously.

Formula:
  I_D = I_DSS × (1 + I_D × R_S / V_P)^2
  Let x = I_D in mA.
  x = 5 × (1 + x×1000 / (-4000))^2
  x = 5 × (1 - x/4)^2

Expand:
  x = 5 × (1 - x/2 + x^2/16)
  x = 5 - 5x/2 + 5x^2/16
  Multiply by 16:
  16x = 80 - 40x + 5x^2
  5x^2 - 56x + 80 = 0

Quadratic formula:
  x = (56 ± √(56^2 - 4×5×80)) / (2×5)
    = (56 ± √(3136 - 1600)) / 10
    = (56 ± √1536) / 10
    = (56 ± 39.2) / 10

  x1 = (56 + 39.2)/10 = 9.52 mA  (reject: exceeds I_DSS = 5 mA)
  x2 = (56 - 39.2)/10 = 1.68 mA  (accept)

  V_GS = -I_D × R_S = -1.68×10^-3 × 1000 = -1.68 V
  V_DS = V_DD - I_D(R_D + R_S) = 15 - 1.68×10^-3 × 3000 = 15 - 5.04 = 9.96 V

Final Answer:
  Q-point: I_D = 1.68 mA, V_GS = -1.68 V, V_DS = 9.96 V

Exam Tip: When solving the self-bias quadratic, you always get two roots. One root gives I_D > I_DSS, which is physically impossible. Always reject that root. The valid Q-point is the smaller I_D value. Also remember: without the bypass capacitor C_S, gain is reduced by the factor (1 + g_m R_S). Many GATE problems ask you to calculate gain with and without C_S. Forgetting the denominator is a frequent error.

Key Properties

• Self-bias requires no negative voltage supply. V_GS is generated automatically by drain current through R_S.
• R_G (typically 1 MΩ) keeps the gate at AC ground without loading the source. No DC current flows through R_G since the gate junction is reverse biased.
• Bypass capacitor C_S (10 µF to 100 µF) must have low reactance at the lowest signal frequency. X_C must be less than R_S/10 at f_min.
• Q-point stability is moderate. I_DSS and V_P vary by 3:1 between devices of the same type, so the actual Q-point shifts between specimens.
• Voltage gain A_v = -g_m R_D with bypass. Without bypass, gain is lower by factor (1 + g_m R_S).
• For a 2N5457 with R_S = 1 kΩ and R_D = 2 kΩ, typical voltage gain is 3 to 5, depending on g_m at the Q-point.

Quick Revision

• Self-bias: V_GS = -I_D × R_S. No negative supply needed.
• Q-point at intersection of self-bias line and parabolic transfer curve.
• Self-bias line passes through origin with slope -1/R_S on V_GS-I_D axes.
• Quadratic gives two roots: reject I_D > I_DSS, keep the smaller root.
• A_v = -g_m R_D with C_S bypassing R_S.
• A_v = -g_m R_D / (1 + g_m R_S) without bypass capacitor.
• R_G = 1 MΩ to avoid loading. Zero DC current flows through R_G.
• Exam trap: Keeping both roots of the quadratic. The root with I_D > I_DSS has no physical meaning and must be discarded. Always check that your answer satisfies 0 < I_D < I_DSS.