Negative Clamper

A negative clamper is a diode-capacitor circuit that shifts the entire AC input waveform downward in the negative direction, so that the most positive point of the output waveform just touches a defined reference level, typically 0V. Like the positive clamper, it preserves the original shape and peak-to-peak amplitude of the signal while adding a negative DC offset. Negative clampers appear in signal processing systems where a waveform must be referenced to a specific lower voltage level.

Core Concept of Negative Clamping

The circuit diagram shows how the reversed diode orientation creates the downward shift, with the output waveform maximum clamped at 0V.

The negative clamper works by the same capacitor charging principle as the positive clamper, but with the diode orientation reversed. In the negative clamper, the diode anode connects to ground and the cathode connects to the node between the capacitor and the output load. This means the diode conducts during the positive half cycle of the input, when the node voltage tries to exceed ground. During this positive half cycle, the capacitor charges with a polarity that opposes the input, and after the first cycle, the stored charge shifts the entire output waveform in the negative direction.

The maximum output voltage is clamped to 0V for an ideal diode, or to +0.7V for a practical silicon diode (the diode forward voltage slightly raises the clamping level). The minimum output is -2Vp (ideal) or -2Vp + 0.7V (practical). The waveform shape is completely preserved. The peak-to-peak amplitude remains 2Vp throughout. The only change is the DC reference point shifts down by Vp.

The capacitor polarity in a negative clamper is opposite to that in a positive clamper. During the conducting half cycle, the capacitor charges with its input-side plate positive and its output-side plate negative. This stored charge then acts as a negative DC source in series with the subsequent input signal, pushing the output voltage downward for all subsequent cycles. This is the fundamental mechanism that causes the downward shift.

Biased Negative Clamper

A biased negative clamper introduces a DC voltage source in series with the diode. If a positive bias voltage V_B is connected in series with the diode (with the positive terminal toward ground side), the clamping level shifts to +V_B + 0.7V instead of 0.7V. This means the positive peaks of the output are now clamped to +V_B + 0.7V, and the entire waveform shifts down by (Vp - V_B - 0.7V). For a negative bias V_B (negative terminal toward ground), the clamping shifts further negative, setting the output peak at -V_B + 0.7V.

Biased clampers are used when a specific DC reference is required at the output. For example, in a radar pulse receiver, the baseline of the received pulse train must be held at a precise voltage to ensure correct amplitude detection. A biased clamper achieves this without any active feedback circuitry. The bias source must have sufficiently low impedance so that it does not significantly change voltage during diode conduction.

Mathematical Expression

For a negative clamper with an ideal diode and input Vin = Vp sin(wt):

Capacitor charges to Vp during first positive half cycle. Output voltage becomes:

Vout = Vin - Vp = Vp sin(wt) - Vp = Vp (sin(wt) - 1)

Maximum output = 0V (at sin(wt) = +1), Minimum output = -2Vp (at sin(wt) = -1). For a silicon diode, capacitor charges to Vp - 0.7V (diode drop reduces charging), giving Vout maximum = +0.7V and minimum = -(2Vp - 0.7V). The DC shift added equals -Vp for an ideal diode.

Practical Understanding

In negative clampers, the load resistor R across the output sets the discharge time constant RC. If RC is too small, the capacitor discharges significantly between cycles, and the clamping level drifts upward over successive cycles until a steady state is reached where the charging current per cycle exactly equals the discharging current. This steady state may not correspond to ideal clamping, causing a shift error. Keeping RC at least 10 times the signal period minimizes this error.

A useful comparison: in a positive clamper, the diode conducts in the negative half cycle; in a negative clamper, the diode conducts in the positive half cycle. This is easy to remember because the diode charges the capacitor during the half cycle that would otherwise push the output in the unwanted direction, and the stored charge then compensates for subsequent cycles in the opposite direction.

Given:
Vin = 12 sin(wt) V  (Vp = 12V, f = 500 Hz, T = 2 ms)
Diode: Silicon (V_D = 0.7V)
Bias: V_B = 2V (positive, in series with diode)
C = 47 uF, R = 47 kOhm
Circuit: Biased negative clamper

Why this formula applies:
Diode conducts when output node tries to exceed V_B + V_D = 2 + 0.7 = 2.7V
Capacitor charges until node voltage = 2.7V
Shift applied = Vp - 2.7 = 12 - 2.7 = 9.3V (downward)

Formula:
Vout_max = V_B + V_D = 2.7V
Vout_min = Vout_max - 2Vp = 2.7 - 24 = -21.3V

Substitution:
At peak input +12V: Vout = +2.7V (clamped)
At trough input -12V: Vout = 2.7 - 24 = -21.3V

RC check: RC = 47 uF x 47 kOhm = 2.209 s >> T = 2 ms (condition well satisfied)

Final Answer:
Output swings from +2.7V to -21.3V
Peak-to-peak = 24V = 2 x Vp (preserved as expected)

Exam Tip: To identify clamper polarity quickly in GATE, look at the diode direction. If the diode can conduct during the positive half cycle (cathode to ground), it is a negative clamper. If it conducts during the negative half cycle (anode to ground), it is a positive clamper. The clamper pushes the waveform opposite to the diode's conduction direction.

Quick Revision

• Negative clamper shifts the output downward so positive peak touches 0V (ideal) or +0.7V (silicon).
• Diode orientation: anode to ground, cathode to signal node. Diode conducts during positive half cycle.
• Output formula: Vout = Vin - Vp (ideal). Vout_max = 0V, Vout_min = -2Vp for ideal diode.
• Silicon diode: Vout_max = +0.7V (diode drop slightly raises clamping level above zero).
• Biased negative clamper: clamping level = V_B + V_D. Waveform peak is held at this value.
• RC time constant must satisfy RC >> T for accurate steady-state clamping.
• Exam trap: Peak-to-peak is always preserved in clampers. Check this to verify your answer.