MOSFET Biasing Techniques

Getting the gate voltage wrong on a MOSFET amplifier stage means distorted output or a device stuck in cutoff. Biasing sets the DC operating point so the transistor stays in saturation across the full signal swing.

Core Concept

The goal of MOSFET biasing is to fix a stable DC drain current ID and drain-source voltage VDS so the device sits in the saturation region. The saturation region is where the MOSFET acts as a controlled current source, which is what amplifier stages require.

For enhancement MOSFETs like the IRF540 or 2N7000, VGS must exceed the threshold voltage Vth (typically 2V to 4V) before any drain current flows. The voltage divider bias method applies a fixed VGS using two resistors from the supply rail. Adding a source resistor RS introduces negative feedback that stabilizes ID against device-to-device variation.

For depletion MOSFETs like the 2N3797, zero-bias works directly: tie gate to source, and the device operates at VGS = 0V with ID = IDSS. This needs no resistor network at all. Voltage divider bias is more common in discrete circuits because it works for both MOSFET types and gives a predictable Q-point.

Key Equations

Gate voltage from divider: V_G = VDD * R2 / (R1 + R2)

Gate-source voltage with source resistor: V_GS = V_G - I_D * R_S

Drain current (enhancement MOSFET, saturation): I_D = K * (V_GS - V_th)^2 where K is the process transconductance parameter in A/V^2 and V_th is threshold voltage.

Drain voltage: V_D = VDD - I_D * R_D

Drain-source voltage: V_DS = V_D - V_S = VDD - I_D*(R_D + R_S)

Saturation condition: V_DS >= V_GS - V_th

Given:
  VDD  = 12 V
  R1   = 100 kΩ
  R2   = 47 kΩ
  RD   = 2.2 kΩ
  RS   = 1 kΩ
  Vth  = 2 V
  K    = 0.5 mA/V^2

Why this formula:
  Enhancement MOSFET in saturation; voltage divider sets VG.

Step 1 - Gate voltage:
  VG = 12 * 47 / (100 + 47) = 564 / 147 = 3.84 V

Step 2 - VGS equation (two unknowns; use ID = K*(VGS-Vth)^2 and VGS = VG - ID*RS):
  VGS = 3.84 - ID * 1000
  ID  = 0.5e-3 * (VGS - 2)^2

Step 3 - Substitute VGS:
  ID = 0.5e-3 * (3.84 - 1000*ID - 2)^2
  ID = 0.5e-3 * (1.84 - 1000*ID)^2

Let x = ID (in mA): x = 0.5*(1.84 - x)^2
  2x = (1.84 - x)^2
  2x = 3.3856 - 3.68x + x^2
  x^2 - 5.68x + 3.3856 = 0
  x = (5.68 - sqrt(32.26 - 13.54)) / 2
    = (5.68 - sqrt(18.72)) / 2
    = (5.68 - 4.327) / 2
    = 1.353 / 2

Final Answer:
  ID = 0.676 mA
  VGS = 3.84 - 0.676 = 3.164 V
  VDS = 12 - 0.676*(2.2 + 1) = 12 - 2.16 = 9.84 V (saturation confirmed: VDS > VGS - Vth = 1.164 V)

Exam Tip: GATE problems on MOSFET biasing almost always require solving a quadratic from the simultaneous equations ID = K*(VGS-Vth)^2 and VGS = VG - ID*RS. Always pick the lower root; the higher root gives VGS below Vth or pushes the device into triode. Also, if RS = 0, VGS = VG directly and there is no quadratic to solve.

Key Properties

• Voltage divider bias uses R1 and R2 from VDD to set VG independent of the transistor parameters, giving good Q-point stability.
• Source resistor RS provides self-stabilizing negative feedback: if ID rises, VS rises, VGS falls, pulling ID back down.
• Enhancement MOSFET biasing always requires VGS > Vth (e.g. Vth = 2V for 2N7000) to turn the device on.
• Depletion MOSFET self-bias (zero-bias) connects G directly to S, giving VGS = 0V and ID = IDSS with no external bias components.
• For large R1 and R2 values (greater than 1 MΩ), gate current is negligible since MOSFET gate draws essentially zero DC current.
• The Q-point must be in saturation: VDS > VGS - Vth for enhancement, or VDS > VGS - Vp for depletion-mode FETs.

Quick Revision

• Biasing goal: fix IDQ and VDSQ in saturation for linear amplification.
• VG from divider: VG = VDD * R2 / (R1 + R2).
• VGS = VG - ID*RS when source resistor is present.
• Enhancement MOSFET: needs VGS > Vth. No self-bias possible.
• Depletion MOSFET: self-bias at VGS = 0 gives ID = IDSS.
• RS stabilizes Q-point via negative feedback; bypass it with a capacitor for AC gain.
• Saturation check: VDS >= VGS - Vth must be satisfied at the Q-point.
• Exam trap: Students forget to check the saturation condition after solving for IDQ and VDSQ, missing that the device is actually in the triode region at their computed Q-point.