CMOS Inverter Basics

Every chip in your smartphone, laptop, and microcontroller is built from CMOS inverters. This circuit is the building block of all digital logic and consumes power only during switching, not while sitting idle.

Core Concept

A CMOS inverter uses one PMOS and one NMOS transistor connected in series between VDD and GND, with both gates driven by the same input. When Vin = 0V (logic LOW), the NMOS is OFF and the PMOS is ON, pulling Vout up to VDD. When Vin = VDD (logic HIGH), the NMOS is ON and the PMOS is OFF, pulling Vout down to 0V.

The brilliance of CMOS is that in both static states, one transistor is always OFF. No DC current path exists from VDD to GND. Static power dissipation is essentially zero (only nanoamp leakage). This contrasts sharply with older NMOS or TTL logic, which drew milliamps of quiescent current. The switching threshold VM is the input voltage at which Vout = Vin, ideally at VDD/2 when the PMOS and NMOS are matched.

Power is only consumed during switching transitions. As Vin crosses VM, both transistors are momentarily ON together, creating a brief short-circuit current spike from VDD to GND. This dynamic power, plus the energy to charge and discharge load capacitance, dominates the power budget of CMOS digital circuits at high frequency.

Key Equations

Static power: P_static ≈ 0 (one transistor always OFF in steady state)

Dynamic power: P_dynamic = C_L * VDD^2 * f where C_L is load capacitance in farads, VDD is supply voltage, and f is switching frequency.

Switching threshold: V_M = (VDD/2) when NMOS and PMOS are symmetrically sized (equal Kn and Kp after accounting for mobility difference).

Noise margin HIGH: NMH = VOH - VIH; Noise margin LOW: NML = VIL - VOL

Propagation delay: t_pd = 0.69 * R_on * C_L where Ron is the on-resistance of the driving transistor.

Given:
  VDD  = 5 V
  CL   = 10 pF  (load capacitance)
  f    = 100 MHz  (switching frequency)

Why this formula:
  Dynamic power = energy per cycle times frequency.
  Energy per cycle = CL * VDD^2.

Formula:
  P_dynamic = CL * VDD^2 * f

Substitution:
  P_dynamic = 10e-12 * (5)^2 * 100e6
            = 10e-12 * 25 * 100e6

Calculation:
  = 10e-12 * 25e8
  = 250e-4
  = 25 mW

Final Answer:
  P_dynamic = 25 mW per inverter at 100 MHz

Note: Scaling VDD to 3.3V reduces power to:
  P = 10e-12 * (3.3)^2 * 100e6 = 10.89 mW  (56% less power)

Exam Tip: GATE tests P_dynamic = CL*VDD^2*f repeatedly. Note that power scales with VDD squared, so halving VDD reduces power by 4 times. Students often write P = CL*VDD*f, forgetting the squared term. Also note: this formula is for one switching event per cycle. For a 0-to-1 and 1-to-0 transition each cycle, some textbooks write P = CL*VDD^2*f with f representing toggle frequency, not clock frequency.

Key Properties

• Static power dissipation is essentially zero because one transistor is always OFF in steady state.
• Dynamic power dissipation is CL*VDD^2*f; it increases linearly with frequency and quadratically with supply voltage.
• The switching threshold VM is ideally at VDD/2, achieved by sizing PMOS wider than NMOS to compensate for lower hole mobility.
• Output voltage swings rail-to-rail: VOH = VDD and VOL = 0V in ideal CMOS.
• Noise margins are large and equal to approximately VDD/2 when VM = VDD/2.
• Short-circuit current flows briefly during transitions when both transistors conduct, adding to dynamic power.
• The CD4007 IC contains three complementary MOSFET pairs and is commonly used for CMOS inverter demonstrations in the lab.

Quick Revision

• Vin = 0: PMOS ON, NMOS OFF, Vout = VDD.
• Vin = VDD: NMOS ON, PMOS OFF, Vout = 0.
• Static power ≈ 0 (no DC path from VDD to GND).
• Dynamic power: P = CL * VDD^2 * f.
• VM ≈ VDD/2 for symmetric sizing.
• Full rail-to-rail output swing: VOH = VDD, VOL = 0.
• Used as the fundamental logic gate in all modern CMOS ICs.
• Exam trap: Students write P = CL*VDD*f (missing the squared exponent on VDD), underestimating power by a factor of VDD (typically 5x or 3.3x off).