CMOS Basic

The CMOS inverter (Complementary Metal-Oxide-Semiconductor inverter) is the foundational logic gate in digital integrated circuit design. It achieves low static power dissipation by using one NMOS and one PMOS transistor in series, ensuring that only one device conducts at a time in steady state. This topic is essential for GATE and forms the conceptual basis for all CMOS digital design.

Core Concept: CMOS Inverter Structure

A CMOS inverter consists of exactly two transistors: a PMOS pull-up transistor and an NMOS pull-down transistor. Both transistors have their gates connected to the input voltage Vin. The PMOS source is connected to VDD, and the NMOS source is connected to GND. The drains of both transistors are connected together and form the output node Vout. This complementary arrangement ensures that exactly one transistor is on and the other is off in each steady-state logic level.

When Vin is LOW (near 0 V), the gate-to-source voltage of the PMOS (VGSp = Vin - VDD) is sufficiently negative to turn the PMOS on (|VGSp| > |VTp|). Simultaneously, the NMOS has VGSn = Vin < VTn, so it is off. The output is pulled to VDD through the PMOS. When Vin is HIGH (near VDD), the NMOS turns on and the PMOS turns off, pulling the output to GND.

The key advantage is near-zero static power dissipation. In both logic states, the series path from VDD to GND is blocked by the off transistor. Current flows only during switching transitions when both transistors may be momentarily conducting. This is why CMOS became the dominant logic family for VLSI: millions of gates can be integrated without exceeding thermal limits.

Mathematical Expression: Switching Threshold

The switching threshold voltage VM of a CMOS inverter is the input voltage at which Vout = Vin (the midpoint of the voltage transfer characteristic). Setting ID_NMOS = ID_PMOS and solving: VM = (VTn + (VDD + VTp) * sqrt(kp/kn)) / (1 + sqrt(kp/kn)), where kn = mu_n*Cox*(W/L)_n and kp = mu_p*Cox*(W/L)_p. For a symmetric inverter where VM = VDD/2, the condition is kn = kp.

Since mu_n is approximately 2 to 3 times mu_p in silicon, achieving kn = kp requires making the PMOS transistor 2 to 3 times wider than the NMOS (Wp/Lp = 2 to 3 times Wn/Ln). This sizing principle is a standard design rule in CMOS layout and appears as a GATE question in the form of asking why PMOS must be wider than NMOS for symmetric operation.

The noise margins of the inverter, NMH = VOH - VIH and NML = VIL - VOL, characterize how much noise on the input can be tolerated before the output changes incorrectly. For an ideal inverter, VOH = VDD, VOL = 0, and VIH and VIL are found from the points where the slope of the voltage transfer characteristic equals -1.

Practical Understanding

Dynamic power dissipation in CMOS is P = alpha * CL * VDD^2 * f, where alpha is the activity factor (probability of a switching event per clock cycle), CL is the load capacitance, VDD is the supply voltage, and f is the clock frequency. This equation is fundamental in low-power design: reducing VDD quadratically reduces power, which is the primary motivation for technology scaling to lower supply voltages.

Short-circuit current flows during a transition when both PMOS and NMOS are simultaneously on for a brief interval around VM. This contributes to total power but is usually smaller than the dynamic component for well-designed circuits with fast signal edges.

Given:
VDD = 1.8 V
VTn = 0.4 V, VTp = -0.4 V
kn = 500 uA/V^2
kp = 200 uA/V^2

Why this formula applies:
VM is where NMOS and PMOS carry equal current with Vout = Vin.

Formula:
VM = (VTn + (VDD + VTp) * sqrt(kp/kn)) / (1 + sqrt(kp/kn))

Substitution:
sqrt(kp/kn) = sqrt(200/500) = sqrt(0.4) = 0.632
Numerator = 0.4 + (1.8 - 0.4) * 0.632
           = 0.4 + 1.4 * 0.632
           = 0.4 + 0.885 = 1.285
Denominator = 1 + 0.632 = 1.632

Calculation:
VM = 1.285 / 1.632 = 0.787 V

Final Answer:
VM = 0.787 V (below VDD/2 = 0.9 V because kn > kp, NMOS stronger)

Exam Tip: For a symmetric CMOS inverter VM = VDD/2, the condition is kn*(W/L)_n = kp*(W/L)_p. Since mu_n > mu_p, PMOS must have a larger W/L. If you are given equal W/L devices, VM shifts below VDD/2 because the stronger NMOS pulls output low at a lower Vin.

• Vin LOW: PMOS on (|VGSp| > |VTp|), NMOS off, Vout = VDD.
• Vin HIGH: NMOS on (VGSn > VTn), PMOS off, Vout = 0.
• Static power = 0 (ideal); dynamic power = alpha*CL*VDD^2*f.
• Symmetric inverter (VM = VDD/2) requires kp*(W/L)_p = kn*(W/L)_n.
• VTC slope = -1 at VIH and VIL defines noise margin boundaries.

Quick Revision

• CMOS inverter = PMOS (pull-up) + NMOS (pull-down) with gates tied to input, drains tied to output.
• Static power = 0 in ideal CMOS; dynamic power = alpha*CL*VDD^2*f.
• Switching threshold: VM = (VTn + (VDD+VTp)*sqrt(kp/kn)) / (1 + sqrt(kp/kn)).
• For VM = VDD/2: kn = kp, which requires Wp/Lp = (mu_n/mu_p)*(Wn/Ln), typically 2-3x wider PMOS.
• Noise margins: NMH = VOH - VIH, NML = VIL - VOL.
• CMOS scales well: smaller VDD reduces power quadratically.
• Exam trap: PMOS turns ON when Vin is LOW because VGSp = Vin - VDD is negative and |VGSp| > |VTp|. This sign convention is frequently confused.