Sample and Hold Circuit

Every analog-to-digital converter needs a stable input while it converts. A sample and hold circuit freezes a rapidly changing analog voltage at a precise instant, giving the ADC time to finish its conversion without chasing a moving target. The LF398 is the industry-standard IC for this function.

Core Concept

During the sample phase, the switch closes and the hold capacitor charges to the input voltage. The capacitor voltage follows Vin with a time constant set by the switch on-resistance and CH. For the LF398, this acquisition time is typically under 4 µs for a 0.1% settling error.

When the control signal opens the switch, the capacitor is isolated from the input. The droop rate then becomes the key performance metric. Leakage current from the switch and op-amp bias current slowly discharge CH, causing the held voltage to drift. A low-bias-current op-amp like the TL071 (50 pA bias) minimizes this.

The aperture time is the delay between the hold command and the actual switch opening. Any input change during aperture time creates an error. In a 12-bit ADC running at 100 kSPS, aperture jitter must be kept below 1 ns to avoid significant quantization errors.

Key Equations

Acquisition time (time to charge CH through switch resistance Ron):

Tacq = 2.3 × Ron × CH × (n + 1) where n is the resolution in bits, Ron is switch on-resistance in Ω, CH in farads.

Droop rate (voltage loss per unit time during hold):

dV/dt = Ileak / CH where Ileak is total leakage current in amperes, CH in farads. Result is V/s.

Hold step error (voltage jump when switch opens due to charge injection):

ΔV = Qinj / CH where Qinj is the charge injected by the gate capacitance of the JFET switch.

Given:
  Hold capacitor CH = 10 nF = 10 × 10^-9 F
  Op-amp bias current Ibias = 50 pA = 50 × 10^-12 A
  Switch leakage Ileak = 10 pA = 10 × 10^-12 A
  Total leakage = 60 pA
  Hold time required = 100 µs

Why this formula:
  During hold phase, leakage current discharges CH, causing voltage droop.

Formula:
  Droop = (Ileak × t) / CH

Substitution:
  Droop = (60 × 10^-12 × 100 × 10^-6) / (10 × 10^-9)

Calculation:
  Numerator = 60 × 10^-12 × 100 × 10^-6 = 6 × 10^-15
  Droop = 6 × 10^-15 / 10 × 10^-9 = 6 × 10^-7 V = 0.6 µV

Final Answer:
  Voltage droop over 100 µs hold time = 0.6 µV
  This is negligible for a 5V full-scale 12-bit ADC (LSB = 1.22 mV).

Exam Tip: GATE problems on S/H circuits most often test droop rate using dV/dt = Ileak/CH. Students confuse acquisition time with aperture time. Acquisition time is how long the capacitor needs to charge to within 0.1% of Vin. Aperture time is the uncertainty in when the switch actually opens. Both cause errors but through different mechanisms. Also note that increasing CH reduces droop but increases acquisition time, so a trade-off always exists.

Key Properties

• The LF398 IC provides a typical acquisition time of 4 µs to 0.01% accuracy with an external 1 nF hold capacitor.
• Droop rate is dominated by op-amp input bias current. The TL071 at 50 pA gives far less droop than a general-purpose LM741 at 80 nA.
• Hold capacitor CH is typically 1 nF to 100 nF. Smaller values give faster acquisition but higher droop and more charge-injection error.
• The JFET switch on-resistance Ron is typically 30 Ω to 200 Ω and directly sets the RC charging time constant.
• Aperture jitter of 1 ns limits accurate sampling of a 1 MHz sine wave to about 9 bits of resolution.
• The buffer op-amp must be in unity-gain configuration to prevent loading of the hold capacitor during the hold phase.
• Charge injection from the JFET gate creates a fixed hold-step error that can be partially corrected by a matched dummy switch.

Quick Revision

• S/H circuit freezes an analog voltage to allow ADC conversion without input movement.
• Two phases: sample (SW closed, CH charges) and hold (SW open, CH holds voltage).
• Droop rate = Ileak / CH in V/s. Lower leakage and larger CH both reduce droop.
• Acquisition time = 2.3 × Ron × CH × (n+1) for n-bit accuracy.
• LF398 is the standard S/H IC. TL071 is preferred as the buffer for low bias current.
• Hold step error comes from charge injection when the switch opens. It shifts the held voltage by ΔV = Qinj/CH.
• Aperture jitter causes sampling uncertainty. Smaller jitter allows accurate sampling of higher-frequency signals.
• Exam trap: Students often increase CH to reduce droop without realizing it proportionally increases acquisition time, which may violate the sampling rate requirement.