Parasitic Extraction

After a VLSI layout passes DRC and LVS, the circuit is not yet ready for final sign-off. The physical wires, contacts, and device geometry introduce parasitic resistances and capacitances that were not present in the ideal pre-layout schematic. These parasitics slow down signal transitions, cause voltage drops on power rails, and can even cause signal integrity failures. Parasitic extraction quantifies these effects so that post-layout simulation can verify that the design still meets its timing and functional specifications.

Core Concept: Why Parasitics Exist

Every metal wire has a finite resistivity and a physical geometry, so it behaves as a distributed RC transmission line rather than an ideal zero-resistance conductor. The wire resistance is determined by the sheet resistance of the metal layer and the aspect ratio (length to width) of the wire. Thinner and longer wires have higher resistance. For global wires at 7 nm nodes, wire resistance dominates over transistor on-resistance, making interconnect the primary delay bottleneck.

Wire capacitance arises from two sources. The first is parasitic capacitance to ground (C_gnd), which comes from the parallel plate capacitance between the wire and the substrate or lower metal layers. The second is coupling capacitance (C_coupling), which is the capacitance between two adjacent wires on the same or neighboring metal layers. Coupling capacitance is critical because a fast-switching aggressor net can inject transient current into a victim net through this capacitance, causing an unwanted voltage glitch.

Device parasitics also exist: the source and drain junctions of each transistor introduce junction capacitances, and the interconnect between the gate and the driver adds gate resistance. The total net capacitance seen at any output node is the sum of the intrinsic device capacitances plus all interconnect capacitances. This total capacitance determines the RC delay and the dynamic power consumption of that net.

Mathematical Expression: RC Extraction Formulas

Wire resistance is computed from sheet resistance: R_wire = R_sq x (L / W), where L is wire length and W is wire width. Wire capacitance to ground is approximated as C_gnd = epsilon_0 x epsilon_r x (W x L) / d, where d is the dielectric thickness below the wire. These are first-order approximations. More accurate extraction uses 3D field solvers (FastCap, Raphael) that account for fringing fields, which can increase capacitance significantly for narrow wires with tall sidewalls.

The Elmore delay model is the standard analytical method for computing delay through an RC tree. For a single RC segment, the delay tau = R x C. For a chain of N segments, the total delay is the sum of R_i x C_downstream_i, where C_downstream_i is the total capacitance driven by segment i. GATE questions often ask for the delay of a simple RC chain, and the Elmore model is always the correct tool.

Practical Understanding: SPEF and Post-Layout Simulation

After layout is complete, a dedicated parasitic extraction tool (Calibre xRC, StarRC, or PVS-R) reads the GDS-II file and computes all R and C values for every net. These values are written into a Standard Parasitic Exchange Format (SPEF) file or a Detailed Standard Parasitic Format (DSPF) file. The SPEF file is then read by a SPICE simulator alongside the netlist to perform post-layout simulation.

Post-layout simulation is almost always slower than pre-layout simulation because the netlist is significantly larger. A 1000-transistor design might expand to a 100,000-element RC netlist after extraction. Designers often use reduced-order models (lumped RC, pi-models) to keep simulation tractable while maintaining accuracy sufficient for timing verification. Static timing analysis (STA) tools like Tempus or PrimeTime use the extracted parasitics to compute setup and hold time slack on every path.

Numerical Example

Given:
Metal-2 wire: Length L = 200 μm, Width W = 0.5 μm
Metal-2 sheet resistance R_sq = 0.08 Ω/sq
Metal-2 capacitance per unit length C_per_um = 0.2 fF/μm
Load capacitance at end of wire C_load = 10 fF
Driver output resistance R_drv = 500 Ω

Why this formula applies:
Elmore delay for a wire with distributed RC + lumped load.

Formula:
R_wire = R_sq × (L / W)
C_wire = C_per_um × L
Elmore delay ≈ R_drv × (C_wire + C_load) + (R_wire × C_wire / 2)

Substitution:
R_wire = 0.08 × (200 / 0.5) = 0.08 × 400 = 32 Ω
C_wire = 0.2 fF/μm × 200 μm = 40 fF
Elmore delay = 500 × (40f + 10f) + (32 × 40f / 2)
             = 500 × 50×10⁻¹⁵ + 16 × 40×10⁻¹⁵

Calculation:
= 25×10⁻¹² + 0.64×10⁻¹² = 25.64 ps

Final Answer:
Elmore delay = 25.64 ps
Wire resistance contributes only 0.64 ps; driver + wire capacitance dominate at 25 ps.
For global 200 μm wires this delay is significant at 1 GHz operation.

Exam Tip: In GATE problems involving RC delay, always split the delay into driver-capacitance term (R_drv × C_total) and wire-resistance term (R_wire × C_wire / 2 for distributed RC). Forgetting the factor of 1/2 for distributed wire RC is a very common mistake. For a lumped RC model, no 1/2 factor is used.

Mechanism: Types of Parasitic Capacitance

• Area capacitance (C_area) comes from the bottom surface of the wire acting as a parallel plate capacitor with the lower conductor. It scales with wire area (W x L).
• Fringe capacitance (C_fringe) comes from the wire sidewall edges. At advanced nodes (below 65 nm), fringe capacitance exceeds area capacitance due to the high aspect ratio of narrow, tall metal wires.
• Coupling capacitance (C_coupling) between adjacent wires causes crosstalk. The crosstalk noise voltage on a victim net is approximately Cc / (Cc + C_victim) times the aggressor switching voltage.
• The SPEF file contains all R, C, and CC values per net. It is annotated back onto the netlist for post-layout SPICE simulation and STA (static timing analysis).
• Elmore delay for a distributed RC wire is (R_wire x C_wire) / 2, not R_wire x C_wire. This factor of 1/2 reflects the distributed nature of the RC — charge at the far end of the wire accumulates gradually, not all at once.

Quick Revision

• Parasitics = R and C from physical interconnect not present in ideal schematic. Must extract before final timing sign-off.
• R_wire = R_sq × (L/W). C_wire = C_per_area × (W × L) + fringe + coupling terms.
• Elmore delay for distributed RC wire = (R × C) / 2. For lumped RC: delay = R × C (no 1/2).
• SPEF file carries extracted R and C values. Fed to SPICE and STA tools for post-layout simulation.
• Coupling capacitance causes crosstalk. Crosstalk noise voltage = Cc / (Cc + C_victim) × aggressor ΔV.
• Exam trap: Fringe capacitance dominates at advanced nodes, not area capacitance. Do not assume C scales only with W × L at sub-65 nm.
• Post-layout simulation is mandatory: pre-layout sim ignores wire R and C. A circuit that passes pre-layout sim can fail timing after extraction.