DRC LVS

After a physical layout is drawn, it must pass two critical verification steps before it can be submitted for fabrication: Design Rule Check (DRC) and Layout Versus Schematic (LVS). DRC ensures that the layout obeys every geometric constraint imposed by the foundry. LVS ensures that the layout actually implements the circuit the designer intended. Both checks are mandatory, and a single failure in either can result in a non-functional chip after fabrication.

Core Concept: Design Rule Check (DRC)

DRC is a purely geometric verification. It takes the layout database (GDS-II file) and checks every polygon against the foundry-supplied rule deck. The rule deck is a technology file that specifies hundreds of constraints such as minimum wire width, minimum spacing between features on the same layer, minimum enclosure of contacts, maximum density of each layer, and antenna rules for gate protection during plasma etching.

A DRC tool like Calibre DRC or Mentor Calibre processes the layout hierarchically and flags every violation as a coordinate-tagged error. The designer must fix each error before proceeding. Some errors are manufacturing-critical (a wire that is too narrow will open-circuit), while others are yield-related (a metal density violation causes non-uniform CMP polishing, leading to thickness variations that can cause shorts).

The antenna rule is a special DRC rule that deserves mention. During plasma etching, long metal wires connected to transistor gates can accumulate charge. If this charge exceeds the gate oxide breakdown voltage, the transistor is permanently damaged. The antenna rule limits the ratio of metal area to gate oxide area on a given net. Violations are fixed by inserting diodes near the gate or breaking the long wire with a higher-metal-layer jog.

Core Concept: Layout Versus Schematic (LVS)

LVS extracts a netlist directly from the layout by identifying all transistors (wherever poly crosses active) and all their connections (traced through metal, contacts, and vias). This extracted netlist is then compared to the reference schematic netlist, which is the intended design. The comparison checks that every device, every node, and every connection matches exactly.

The LVS tool uses a process called netlist flattening and then node matching. It assigns device fingerprints based on type (NMOS/PMOS), size (W/L ratio), and connections. It then attempts to find a one-to-one mapping between schematic and layout devices. If a transistor is missing, a contact is absent (creating an open net), or two nets are accidentally shorted, LVS reports a mismatch with a description of what is wrong and where.

Mathematical Expression: Antenna Ratio

The antenna ratio is defined as the ratio of the cumulative metal area connected to a gate to the gate oxide area. The foundry specifies a maximum permissible antenna ratio, typically between 200 and 400. If this ratio is exceeded, the rule is violated. The formula is straightforward but the implication is physical: charge collected by a large conductor must not exceed what the thin gate oxide can withstand without breaking down.

Numerical Example

Given:
Metal wire connected to a single gate
Metal area (accumulated) = 50 μm²
Gate oxide area (transistor gate) = 0.18 μm × 1 μm = 0.18 μm²
Foundry maximum antenna ratio = 300

Why this formula applies:
Antenna ratio compares charge-collecting area to gate area.
Exceeding the foundry limit risks gate oxide breakdown during plasma etch.

Formula:
Antenna Ratio = Metal Area / Gate Oxide Area

Substitution:
Antenna Ratio = 50 μm² / 0.18 μm²

Calculation:
Antenna Ratio = 277.8

Final Answer:
Antenna Ratio ≈ 278 < 300 (foundry limit)
Result: DRC PASS for antenna rule.
If metal area were 60 μm²: ratio = 333 > 300 → DRC FAIL, fix required.

Exam Tip: DRC is geometric (does the layout obey dimension rules?). LVS is functional (does the layout match the schematic?). Both are required before tape-out. A common exam question asks which check would catch a missing contact wire — the answer is LVS (open net), not DRC, since DRC only checks geometry, not connectivity intent.

Mechanism: LVS Netlist Extraction and Comparison

• DRC checks geometry against foundry rules. It does not know what the circuit is supposed to do. It only verifies that every polygon satisfies manufacturing constraints.
• LVS checks connectivity and device correctness. It extracts transistors and nets from the layout and compares them to the schematic. A DRC-clean layout can still fail LVS if a contact is missing.
• Antenna rule is a DRC rule that protects gate oxide from plasma charge accumulation during fabrication. It is checked by comparing metal area to gate oxide area on each net.
• Common LVS errors include open nets (missing contact or wire), shorts (two nets accidentally connected), wrong device size (W/L mismatch), and floating gates (unconnected gate terminals, which cause undefined logic states).
• Both DRC and LVS must pass before tape-out. Foundries will not accept a GDS-II file with any DRC errors. LVS errors indicate a functional mismatch that would produce a non-working chip.

Quick Revision

• DRC = geometric verification against foundry rule deck. Checks width, spacing, enclosure, density, and antenna ratio.
• LVS = netlist comparison. Extracted layout netlist must match schematic netlist device-for-device and net-for-net.
• Antenna ratio formula: Antenna Ratio = Metal Area / Gate Oxide Area. Must be below foundry limit (typically 200-400).
• DRC cannot catch a missing contact (open net) because it only checks geometry, not intended connectivity. LVS catches this.
• Exam trap: A layout that passes DRC can still fail LVS. Both checks are independent and both are mandatory.
• Floating gate = gate terminal not connected to any net. This is a critical LVS error since a floating gate causes undefined transistor behavior.
• Tools: Calibre DRC/LVS (Siemens EDA), PVS (Cadence), Hercules (Synopsys) are industry-standard physical verification tools.