Memory Interfacing Interview Questions

Q1. What is memory interfacing and why is it necessary in microprocessor systems?

Memory interfacing is the process of connecting external memory devices to a microprocessor's address, data, and control buses such that the processor can reliably read and write data within its timing requirements. An 8085 microprocessor at 3 MHz has a memory read cycle of about 335 ns, so any SRAM or ROM connected to it must have access time below 300 ns (allowing for bus propagation delays). Without proper interfacing — correct address decoding, chip enable timing, and bus width matching — the processor reads incorrect data or crashes unpredictably.

Follow-up: What is the difference between memory-mapped I/O and I/O-mapped I/O?

Q2. What is address decoding and what are the two main types?

Address decoding is the process of generating chip select signals for individual memory or peripheral devices by decoding the microprocessor's address lines so each device responds only to its assigned address range. Full address decoding uses all address lines to generate unique, non-overlapping select signals (e.g., 74HC138 decoder using A13–A15 for 8 KB pages in an 8085 system), while partial address decoding uses only some lines, creating address aliasing where one device responds to multiple addresses. Intel 8085-based systems often used partial decoding with 74LS138 to reduce component count, accepting address aliasing in single-product designs.

Follow-up: What is address aliasing and when is it acceptable in embedded systems?

Q3. How do you interface an SRAM to an 8085 microprocessor?

To interface a 2 KB SRAM (2114) to the 8085, connect address lines A0–A9 to the SRAM address inputs, the 8-bit data bus to D0–D7, generate the chip select from A10–A15 using a 74LS138 decoder, and connect MEMR bar to OE and MEMW bar to WE of the SRAM. The 8085 ALE signal demultiplexes the lower address byte from the multiplexed AD0–AD7 bus using a 74LS373 latch, which is latched on the falling edge of ALE. The full interface requires 3 ICs (latch, decoder, SRAM) plus a PCB layout ensuring address setup time exceeds the SRAM's minimum address-to-output specification.

Follow-up: Why does the 8085 multiplex its lower address byte with the data bus, and what problem does this create for system designers?

Q4. What is the difference between SRAM and DRAM and which is easier to interface?

SRAM stores each bit in a 6-transistor flip-flop cell that retains data as long as power is applied without refresh, while DRAM stores each bit in a 1-transistor-1-capacitor cell that requires periodic refresh every 4–64 ms to prevent charge leakage. A Cypress CY62256 32 KB SRAM interfaces with a simple OE/WE/CE scheme and access time of 55 ns, while a 64 MB SDRAM requires multiplexed row/column address strobes (RAS, CAS), DQM signals, and a DRAM controller managing refresh cycles automatically. SRAM is dramatically simpler to interface and is preferred in microcontroller systems below 16 MB; DRAM is used only when large memory is needed due to lower cost per bit.

Follow-up: What is CAS latency in SDRAM and how does it affect system performance?

Q5. What is memory-mapped I/O and how does it compare to I/O-mapped I/O?

Memory-mapped I/O assigns peripheral registers addresses within the normal memory address space, allowing peripherals to be read and written using the same MOV/LOAD/STORE instructions as memory, while I/O-mapped I/O uses separate IN/OUT instructions and a dedicated I/O address space (as in Intel x86 and 8085). ARM Cortex-M processors use memory-mapped I/O exclusively — the GPIOA ODR of an STM32F4 lives at address 0x40020014 and is written with a standard STR instruction. Memory-mapped I/O simplifies code (same instructions for memory and peripherals) but consumes address space; I/O-mapped I/O preserves the full memory address space for RAM and ROM.

Follow-up: What is the advantage of memory-mapped I/O in a C program compared to I/O-mapped I/O?

Q6. What is bank switching and why was it used in early microprocessors?

Bank switching is a technique where additional memory chips are selected using I/O port bits or extra address lines to extend the effective address space beyond the processor's physical address bus width. The 8-bit Z80 and 8085 have 16-bit address buses limited to 64 KB, but systems like the CP/M computer used bank switching with I/O port bits to select one of four 16 KB RAM banks, achieving 64 KB per bank × 4 banks = 256 KB total. Modern microcontrollers with 32-bit address buses (4 GB space) do not need bank switching, but it remains relevant in 8-bit microcontrollers used in cost-sensitive designs.

Follow-up: What is the extended indirect addressing mode in the 8051 (MOVX instruction) and how does it relate to external memory banking?

Q7. What are the timing parameters critical in memory interfacing?

The three critical parameters are access time (tACC): the delay from address stable to valid data out, which must be less than the processor's memory read cycle time; output hold time (tOH): how long data remains valid after address changes, preventing bus contention; and cycle time (tRC): minimum time between successive read operations, preventing back-to-back accesses that corrupt data. A 70 ns SRAM interfaced to an 8085 at 6 MHz must have tACC < 240 ns (8085 read cycle minus setup margins), which the 70 ns part easily satisfies. Violating setup or hold time requirements causes intermittent read errors that are extremely difficult to debug without a logic analyzer.

Follow-up: What is the purpose of wait states in memory interfacing and how are they generated?

Q8. How does NOR Flash differ from NAND Flash in terms of interfacing?

NOR Flash provides random byte-addressable read access using a parallel address/data bus interface, making it directly executable-in-place (XIP) by a microprocessor, while NAND Flash uses a serial command/address/data multiplexed interface with page-based access, requiring a NAND controller and cannot be directly executed from. An STM32F4 executes code directly from its internal NOR-type Flash at the AHB bus address 0x08000000 without any controller, while an SD card using NAND Flash requires an SPI/SDIO controller and FAT filesystem driver. NOR Flash has lower density and higher cost per bit but is essential for code storage in microcontrollers.

Follow-up: What is wear leveling in NAND Flash and why is it needed?

Q9. What is the role of the ALE signal in 8085/8051 memory interfacing?

ALE (Address Latch Enable) is a positive pulse generated by the 8085/8051 at the beginning of each bus cycle to indicate that the multiplexed AD0–AD7 bus carries valid address information; an external latch (74LS373) captures this address on ALE's falling edge, holding it stable during the data phase. Without the ALE latch, the lower 8 address bits would be lost when the AD bus switches to carry data, making external memory interfacing impossible. On the 8051, PSEN bar (Program Store Enable) and ALE together control the external code memory fetch cycle in a similar manner.

Follow-up: What is the difference between PSEN bar and RD bar on the 8051 and which signal selects code versus data memory?

Q10. What is the 74LS138 decoder and how is it used for memory address decoding?

The 74LS138 is a 3-to-8 line decoder with active-low outputs and three enable inputs (G1, G2A bar, G2B bar), converting a 3-bit binary address on inputs A, B, C to one of 8 active-low chip select outputs. In an 8085 system, connecting A13, A14, A15 to the 74LS138 inputs and MEMR bar to G2A creates 8 non-overlapping 8 KB memory windows (0000H–1FFFH, 2000H–3FFFH, …, E000H–FFFFH), each activated by the corresponding output (Y0–Y7). Multiple 74LS138s can be cascaded, using an outer decoder to select groups and inner decoders for finer granularity in systems requiring many memory-mapped peripherals.

Follow-up: How would you modify the 74LS138-based decoder to create a scheme where only I/O cycles activate the chip selects?

Q11. What is DMA and how does it relate to memory interfacing?

DMA (Direct Memory Access) allows a peripheral controller to transfer data directly between a device and memory without CPU involvement, using the processor's address and data buses by temporarily taking over bus control from the CPU through HOLD/HLDA handshake. An 8257 DMA controller connected to an 8085 enables a disk controller to write 512 bytes directly into SRAM in about 50 μs at 1 MB/s, compared to 500 μs if each byte required a CPU interrupt service. Modern ARM-based microcontrollers like STM32 have internal DMA controllers integrated in the AHB/APB bus matrix, eliminating the need for external DMA chips.

Follow-up: What is the HOLD/HLDA handshake in the 8085 and how does it enable DMA operation?

Q12. How do you calculate the memory map of an 8085 system with multiple devices?

The memory map is derived by fixing which address lines are decoded by the chip select logic, then determining which address combinations activate each device's chip enable — each device occupies a contiguous block whose size equals 2^(number of undecoded address lines). If A15, A14 drive a 74LS138 and A0–A13 are the device address lines, each device occupies 2^14 = 16 KB starting at 0000H, 4000H, 8000H, C000H, giving a clean 4-region map for a 64 KB 8085 system. Overlaps occur with partial decoding (if fewer than all high address bits are decoded), which must be documented to avoid writing to multiple devices simultaneously.

Follow-up: Draw the memory map of an 8085 system with one 8 KB ROM at 0000H and one 8 KB RAM using 74LS138 full decoding.

Q13. What is the difference between ROM, EPROM, EEPROM, and Flash memory in terms of write and erase mechanisms?

ROM is mask-programmed at the factory and cannot be changed; EPROM (UV-erasable, e.g., 27C256) is electrically programmed with 12.5 V pulses and erased by UV light through a quartz window; EEPROM allows byte-level electrical erase and rewrite at circuit voltage but is slower (ms per byte) and more expensive than Flash; Flash (e.g., Winbond W25Q128) uses sector/block erase with page-program, offering high density at lower cost but requiring erase before rewrite. The AT89S52 8051 uses internal ISP Flash (8 KB) that can be reprogrammed over SPI without removing from the circuit, replacing the earlier UV-erasable EPROM versions. Flash endurance is rated at 10,000–100,000 erase cycles, after which cells fail to retain data.

Follow-up: What is the minimum unit of erase operation in NOR Flash and NAND Flash?

Q14. How is external memory interfaced to an ARM Cortex-M microcontroller using the FSMC?

The FSMC (Flexible Static Memory Controller) in STM32F2/F4 provides a configurable parallel bus supporting SRAM, NOR Flash, NAND Flash, and LCD interfaces, with up to 4 independent chip select regions (Bank 1–4) each 64 MB and timing parameters (address setup, data hold, bus turnaround) configurable in registers. Connecting a 16-bit SRAM (IS61WV5128) to FSMC Bank 1 uses address lines A0–A18, data lines D0–D15, NE1 as chip enable, NOE as read enable, and NWE as write enable, with the mapped base address at 0x60000000. The FSMC makes the external SRAM appear as normal addressable memory, allowing C array accesses without custom bus timing code.

Follow-up: What is the difference between FSMC and FMC in STM32 microcontrollers?

Q15. What is cache memory and does it appear in microcontroller memory interfacing?

Cache memory is a small, fast SRAM placed between the processor core and the main memory, storing recently used instructions and data to reduce the average memory access latency, and is found in Cortex-M7 (16 KB I-cache + 16 KB D-cache) and some high-end Cortex-M4 devices. An STM32H743 Cortex-M7 running at 480 MHz accesses its internal Flash at only 70 MHz, making the instruction cache critical to achieve full CPU throughput — without it, the CPU would stall 6 out of 7 cycles waiting for Flash. Cache memory introduces coherency challenges in DMA-based systems where DMA writes to a memory region the CPU has cached, requiring explicit cache invalidation before reading DMA results.

Follow-up: What is a cache invalidation and when must you perform it in an STM32H7 DMA application?