Space Vector Modulation

Concept of reference vector synthesis.

Darshan N
Updated: 7 April 2026
9 min read

Space Vector Modulation treats the three phase inverter as a single unit to generate a rotating voltage vector. It is the standard modulation technique for modern variable frequency drives.

V1(100)V2(110)V3(010)V4(011)V5(001)V6(101)Vref
Space vector diagram showing 6 active vectors.

Core Concept

The inverter states map to six active vectors and two zero vectors. These vectors form a hexagon in the complex plane. The reference vector rotates inside this hexagon at the desired fundamental frequency.

The controller approximates the reference vector by switching between adjacent active vectors and zero vectors. The duty cycles are calculated based on volt second balance. A typical switching frequency is 10 kHz.

SVM maximizes the utilization of the DC bus voltage. It generates 15 percent more fundamental voltage than standard sinusoidal PWM. It also optimizes the placement of zero vectors to minimize switching losses.

Key Formulas

Maximum phase voltage amplitude = Vdc / sqrt(3). Modulation index ranges from 0 to 1.15 compared to SPWM. Switching time calculations use trigonometric projections.

Example
Given: Vdc = 500 V, Maximum linear modulation.
Formula: Vline_max = Vdc, Vphase_max = Vdc / sqrt(3).
Steps:
1. Vline_max = 500 V.
2. Vphase_max = 500 / 1.732 = 288.6 V.
Final Answer: Maximum linear phase voltage = 288.6 V.
Exam Tip: SVM utilizes the DC link voltage 15.5 percent better than standard SPWM. The maximum peak phase voltage is Vdc divided by square root of 3.

Performance Parameters

  • DC bus utilization is maximized compared to other techniques.
  • Total harmonic distortion is lower than SPWM.
  • Switching losses are reduced by optimal zero vector placement.
  • Computationally intensive due to trigonometric calculations.
  • Excellent for digital implementation in microcontrollers.

Quick Revision

  • Uses eight base voltage vectors.
  • Hexagon boundary defines the linear modulation region.
  • Volt second balance determines vector dwell times.
  • Generates less current ripple than SPWM.
  • Standard in field oriented control systems.
  • Exam trap: Confusing the maximum line voltage and phase voltage limits in SVM.

Space Vector Modulation

Assess reference vectors and DC bus utilization limits.

Question 1 of 3

Q1.How many non-zero active voltage vectors are geometrically generated by the eight possible switching states of a standard two-level, three-phase VSI?