I2C

The I2C protocol, short for Inter-Integrated Circuit, is a synchronous serial communication standard widely used to connect low-speed peripherals like sensors, EEPROMs, and display controllers to a microcontroller. It uses only two wires for communication, making it highly economical in terms of pin usage. Understanding I2C is essential for embedded systems design and is a frequently tested topic in GATE Electronics.

Core Concept of I2C

The I2C protocol uses two bidirectional open-drain lines: the Serial Clock Line (SCL) and the Serial Data Line (SDA). The master generates the clock on SCL and initiates all transactions. Because both lines are open-drain, external pull-up resistors are required to keep the bus in the idle high state. Any device on the bus can pull the line low but none can drive it high actively.

Each slave device has a unique 7-bit address programmed into it by the manufacturer or through address pins. When the master wants to communicate, it broadcasts a START condition followed by the 7-bit address and a read/write bit. The slave that recognizes its own address pulls SDA low to send an ACK (Acknowledgement) bit, confirming it is ready. If no slave responds, the master detects a NACK and can abort the transaction.

The START condition is defined as SDA going low while SCL is high. The STOP condition is SDA going high while SCL is high. These two conditions are the only events allowed to change SDA while SCL is high; during normal data transfer, SDA must be stable when SCL is high and can only change when SCL is low.

Addressing and Data Transfer

In standard 7-bit addressing, the first byte sent after START contains the 7-bit slave address in bits 7:1 and the R/W direction bit in bit 0. A 0 in the R/W bit means the master is writing to the slave; a 1 means the master is reading from the slave. After the address byte, an ACK is expected from the slave before data bytes are transferred one byte at a time, each followed by an ACK.

I2C supports 10-bit addressing for systems needing more than 112 slave addresses. In 10-bit mode, a two-byte header is used to encode the extended address. Standard mode supports speeds up to 100 kbps, Fast mode up to 400 kbps, Fast-mode Plus up to 1 Mbps, and High-speed mode up to 3.4 Mbps.

Mathematical Expression

The minimum pull-up resistor value on the I2C bus is determined by the maximum sink current the device can handle. If a device can sink a maximum of 3 mA and the supply voltage is 3.3 V, and the low logic level threshold is 0.4 V, the minimum pull-up resistance is calculated using Ohm's law. The pull-up resistor must be small enough to pull the line high within the rise-time budget and large enough not to exceed the sink current limit.

The formula for minimum pull-up resistance is: R_min = (VCC - VOL_max) / I_OL_max, where VCC is supply voltage, VOL_max is the maximum allowed low output voltage, and I_OL_max is the maximum sink current the weakest driver on the bus can handle.

Given:
VCC = 3.3 V
VOL_max = 0.4 V (maximum low level output voltage)
I_OL_max = 3 mA (maximum sink current of I2C device)

Why this formula applies:
The pull-up resistor must not allow current to exceed the device's sink capability when the line is pulled low.

Formula:
R_min = (VCC - VOL_max) / I_OL_max

Substitution:
R_min = (3.3 - 0.4) / 0.003

Calculation:
R_min = 2.9 / 0.003
R_min = 966.67 Ω

Final Answer: Minimum pull-up resistance required = 967 Ω (use 1 kΩ standard value)

Exam Tip: In GATE problems, the START condition is SDA falling while SCL is HIGH and STOP is SDA rising while SCL is HIGH. These are the two unique bus states that cannot occur during normal data transmission. Do not confuse them with clock edges.

• The START condition initiates every I2C transaction and is the only event where SDA goes low while SCL is already high.
• After START, the master sends an 8-bit frame: 7 address bits and 1 direction bit (0 for write, 1 for read).
• The addressed slave responds with ACK by pulling SDA low during the 9th clock pulse generated by the master.
• NACK (no acknowledgement, SDA left high) indicates the slave is busy, the address was not recognized, or an error occurred.
• The STOP condition releases the bus by letting SDA go high while SCL is high, signaling all slaves that the bus is now free.

Quick Revision

• I2C uses two lines: SCL (clock, master-generated) and SDA (bidirectional data).
• Both lines are open-drain; pull-up resistors to VCC are mandatory.
• 7-bit addressing supports up to 112 usable slave addresses (16 are reserved).
• START: SDA falls while SCL is HIGH. STOP: SDA rises while SCL is HIGH.
• ACK = slave pulls SDA LOW on 9th clock. NACK = SDA remains HIGH.
• Speeds: Standard (100 kbps), Fast (400 kbps), Fast+ (1 Mbps), High-speed (3.4 Mbps).
• Common trap: SDA must NOT change while SCL is HIGH except during START and STOP conditions.