External Interrupts

In embedded systems, a microcontroller must respond to events occurring in the external world, such as a button press, a sensor trigger, or a communication signal. Waiting in a loop to check these events wastes processor cycles. External interrupts allow the processor to continue executing main code and only respond when an external event actually occurs, making systems faster and more power efficient.

Core Concept: What are External Interrupts

An interrupt is a hardware signal that pauses the current execution flow, saves processor state, and transfers control to a predefined function called an Interrupt Service Routine (ISR). After the ISR completes, the processor restores the saved state and resumes from exactly where it stopped.

External interrupts are specifically triggered by signals on GPIO pins. In STM32 microcontrollers, each GPIO pin is mapped to an EXTI line (External Interrupt/Event line). There are 16 EXTI lines (EXTI0 to EXTI15), and each EXTI line can be connected to one pin from any GPIO port, but not to multiple ports simultaneously for the same line number.

For example, EXTI0 can be connected to PA0, PB0, or PC0, but only one of them at a time. The selection is made through the SYSCFG_EXTICSRx register. This multiplexing design reduces hardware complexity while covering all pins.

EXTI Line Configuration

Configuring an external interrupt involves four steps. First, the GPIO pin must be set to input mode. Second, the SYSCFG register maps the pin to the corresponding EXTI line. Third, the trigger type is selected: rising edge, falling edge, or both. A rising edge trigger fires when the signal transitions from low to high, while a falling edge fires on high to low transition.

Fourth, the interrupt must be enabled in the NVIC (Nested Vectored Interrupt Controller). The NVIC manages all interrupts in Cortex-M processors, assigning priority levels and deciding which interrupt executes when multiple are pending simultaneously. A lower priority number means higher urgency.

Mathematical Expression: Interrupt Latency

The time from an external event occurring to the first instruction of the ISR executing is called interrupt latency. For Cortex-M4 processors, the minimum interrupt latency is 12 clock cycles in the best case with no wait states or pipeline stalls. The latency can be calculated as follows:

Latency (seconds) = Number of cycles / System clock frequency. At 84 MHz with 12 cycles minimum latency, the response time is approximately 143 nanoseconds. Any ongoing instruction must complete before the processor saves its context.

Practical Understanding

In real applications, external interrupts are used for push-button inputs, rotary encoder pulses, zero-crossing detection in power electronics, and external sensor alerts. The ISR should be kept as short as possible. Heavy processing like UART transmission or LCD updates should be deferred to the main loop using a flag variable set inside the ISR.

Debouncing is a critical practical concern. A mechanical button produces multiple transitions when pressed due to contact bounce. This causes multiple ISR triggers for a single press. Software debouncing using a timer or a simple delay check inside the ISR is commonly used to prevent this.

Given:
System clock = 72 MHz
Minimum Cortex-M3 interrupt latency = 12 clock cycles

Why this formula applies:
Interrupt latency determines how quickly hardware can respond to real-world events.

Formula:
Latency (ns) = (Latency cycles / Clock frequency) x 10^9

Substitution:
Latency = (12 / 72,000,000) x 10^9

Calculation:
Latency = (12 / 72) x 1000 ns
Latency = 0.1667 x 1000 ns

Final Answer:
Minimum interrupt latency = 166.7 ns at 72 MHz system clock

Exam Tip: EXTI lines 5-9 share one IRQ handler (EXTI9_5_IRQHandler) and lines 10-15 share another (EXTI15_10_IRQHandler). Inside the shared handler, check the pending bit to identify which line triggered. This is a common MCQ trap.

EXTI Configuration Flow

• EXTI lines 0-15 correspond to GPIO pin numbers 0-15 across all ports.
• Only one GPIO port can be mapped to a given EXTI line at a time through SYSCFG.
• Rising edge sets RTSR bit; falling edge sets FTSR bit; both can be set simultaneously.
• The EXTI pending register (PR) must be cleared inside the ISR by writing 1 to the corresponding bit.
• NVIC priority ranges from 0 (highest) to 15 (lowest) on most STM32 devices with 4-bit priority.

Quick Revision

• External interrupts allow GPIO pins to trigger ISR execution on signal edges without polling.
• STM32 has 16 EXTI lines (EXTI0-EXTI15); each maps to one GPIO port via SYSCFG_EXTICRx.
• Trigger types: rising edge (RTSR), falling edge (FTSR), or both.
• EXTI5-9 share one NVIC IRQ; EXTI10-15 share another. Check pending bit inside shared ISR.
• Minimum Cortex-M latency formula: Latency = Cycles / Clock_Hz. At 72 MHz, 12 cycles = 166.7 ns.
• Always clear the EXTI pending register (write 1 to PR bit) at end of ISR to prevent re-entry.
• Keep ISR code minimal; use flags to defer processing to main loop.