Interrupts

Interrupts are one of the most fundamental mechanisms in microprocessor-based systems, enabling the CPU to respond to internal or external events without continuously polling for them. In the 8086 architecture, interrupts allow the processor to pause normal execution, save its state, execute a special service routine, and then resume the original task seamlessly. A thorough understanding of interrupt types, the Interrupt Vector Table, and the INT instruction is essential for both university examinations and GATE.

Core Concept Explanation

An interrupt causes the 8086 to suspend its current execution, save the processor state, and branch to an Interrupt Service Routine (ISR). The processor saves the flags register, CS, and IP onto the stack before jumping to the ISR. When the ISR finishes, the IRET instruction restores all three values, and execution continues from exactly where it was interrupted. This save-and-restore mechanism ensures no program state is lost.

Hardware interrupts originate from external devices. The INTR (Interrupt Request) pin is the maskable hardware interrupt input. It is controlled by the Interrupt Flag (IF) in the FLAGS register. When IF=1, the CPU accepts INTR requests. When IF=0 (using the CLI instruction), INTR is ignored. The NMI (Non-Maskable Interrupt) pin bypasses the IF flag and always forces an interrupt response, making it suitable for critical events like memory parity errors.

Software interrupts are generated by the INT n instruction in the program itself. The value n is an 8-bit type number from 0 to 255. Certain type numbers are reserved: INT 0 is the divide-by-zero exception, INT 1 is the single-step trap (used with the Trap Flag TF), INT 2 is NMI, INT 3 is the breakpoint interrupt (used by debuggers), and INT 4 is the overflow interrupt (triggered by INTO instruction). Types 5 through 255 are available for DOS, BIOS, and user-defined routines.

Interrupt Vector Table Structure

The Interrupt Vector Table (IVT) is a fixed 1 KB region in memory from physical address 00000h to 003FFh. It stores the starting addresses of all 256 ISRs. Each entry occupies exactly 4 bytes: the lower 2 bytes hold the IP (offset) and the upper 2 bytes hold the CS (segment) of the ISR. The table holds 256 such 4-byte entries (256 x 4 = 1024 bytes = 1 KB).

To find the vector table entry for interrupt type n, the CPU computes the physical address as 4 x n. For example, INT 21h maps to physical address 4 x 33 = 84h = 132 decimal. The CPU reads 4 bytes from that address, loads the lower word into IP and the upper word into CS, and begins executing the ISR. This lookup mechanism makes it easy to install custom ISRs by simply writing a new CS:IP pair into the appropriate IVT entry.

Mathematical Expression

The IVT address calculation is straightforward. For interrupt type n, the IVT entry address is 4n. The ISR entry point is read as: IP = Memory[4n], CS = Memory[4n + 2]. The stack usage during an interrupt is 6 bytes: 2 bytes for FLAGS, 2 bytes for CS, and 2 bytes for IP, pushed in that order. The stack pointer SP decreases by 6 during interrupt acknowledgment and increases by 6 when IRET executes.

Practical Understanding

The 8086 uses the 8259A Programmable Interrupt Controller (PIC) to manage multiple hardware interrupt sources through the single INTR pin. The PIC prioritizes up to 8 external interrupt lines (IR0 to IR7) and sends the appropriate interrupt type number to the CPU during the interrupt acknowledge cycle. This allows keyboards, timers, serial ports, and disk controllers to coexist on the same interrupt system.

When writing ISRs, it is important to preserve all registers used inside the routine by pushing them at entry and popping them before IRET. Failing to do so corrupts the state of the interrupted program. Also, for INTR-based hardware ISRs, an End Of Interrupt (EOI) command must be sent to the 8259 before executing IRET, or the PIC will not send any further interrupt requests.

Solved Numerical Example

Find the physical address of the IVT entry for INT 21h, and determine how many bytes are pushed onto the stack when this interrupt is acknowledged.

Given:
Interrupt type number n = 21h = 33 decimal
IVT base address = 00000h

Why this formula applies:
Each IVT entry is 4 bytes wide.
Physical address of entry = 4 x n

Formula:
IVT Address = 4 x n
Stack usage = 6 bytes (FLAGS + CS + IP)

Substitution:
IVT Address = 4 x 33 = 132 decimal

Calculation:
132 decimal = 84h
So IVT entry for INT 21h is at physical address 00084h.
First 2 bytes at 00084h = IP of ISR
Next 2 bytes at 00086h = CS of ISR

Final Answer:
IVT address for INT 21h = 00084h
Stack bytes pushed = 6 bytes (FLAGS, CS, IP in that order)

Exam Tip: IRET pops IP first, then CS, then FLAGS from the stack, which is the reverse of push order. Also, IF and TF are automatically cleared when any interrupt is acknowledged, preventing nested interrupts by default.

• FLAGS, CS, IP are pushed to stack (6 bytes total) when any interrupt occurs.
• IF and TF are cleared automatically after interrupt acknowledgment.
• IVT entry for INT n is at physical address 4n; CS is stored at 4n+2.
• IRET restores IP, then CS, then FLAGS (reverse of push order).
• NMI uses INT 2 vector and cannot be masked by IF.
• For maskable INTR, EOI must be sent to 8259 before IRET.

Quick Revision

• Three interrupt types: Hardware (INTR, NMI), Software (INT n), Internal exceptions.
• IVT occupies 00000h to 003FFh; 256 vectors x 4 bytes = 1 KB.
• IVT address formula: Physical address = 4 x interrupt type number.
• Stack usage per interrupt = 6 bytes (FLAGS + CS + IP).
• INTR is maskable (IF controls it); NMI is non-maskable (always INT 2).
• Reserved vectors: INT 0 = divide error, INT 1 = single step, INT 3 = breakpoint, INT 4 = overflow.
• Exam trap: IRET pops in reverse order: IP first, then CS, then FLAGS.